Magnachip Semiconductor, Inc.

Key Foundry Co., Ltd

In Chul Jung

Jung Hwan Lee

Min Kuck Cho

Myeong Seok Kim

Su Jin Kim

Kyung Ho Lee

Hyun Chul Kim

Hee Baeg An

Young Bae Kim

Seung Guk Kim

A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.

Single poly non-volatile memory device and manufacturing method thereof

A CMOS transistor manufacturing method includes: forming a gate insulating film on a semiconductor substrate; forming a first gate electrode pattern on the gate insulating film in an NMOS transistor area; forming a second gate electrode pattern on the gate insulating film in a PMOS transistor area; forming a first photoresist pattern covering the NMOS transistor area to expose the second gate electrode pattern; performing a first ion injection process into the PMOS transistor area to form an n-type well region and a p-type LDD region; removing the first photoresist pattern; forming a second photoresist pattern covering the PMOS transistor area to expose the first gate electrode pattern; performing a second ion injection process into the NMOS transistor area to form a p-type well region and an n-type LDD region; removing the second photoresist pattern; and forming sidewall spacers at sidewalls of the first and second gate electrode patterns.

Method of manufacturing a CMOS transistor

A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.

Single poly multi time program cell and method of operating the same

An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.

Integrated semiconductor device having isolation structure for reducing noise

Growing community of inventors

Daegu, South Korea

In Chul Jung