Samsung Electronics Co., Ltd.

In-Cheol Shin

Byung-Gil Choi

Gong-Heum Han

Ki-Won Lim

Yu-Hwan Ro

Won-Ryul Chung

Cheol-Sung Park

Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.

Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same

A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.

Nonvolatile memory device using a variable resistive element and associated operating method

A semiconductor memory device is provided which uses an externally applied power supply voltage as its operating voltage. The device comprises plural memory cells each arranged in intersections of word lines and bit lines. The device further comprises an internal power supply voltage generating circuit for receiving the externally applied power supply voltage to generate an internal power supply voltage of a first level. Furthermore, the device has a plurality of word line drivers each connected to the word lines and to a power node for receiving the internal power supply voltage. The each of the word line drivers drives a corresponding word line with the internal power supply voltage in response to a word line selection signal. According to the semiconductor memory device of the present invention, a potential on the word line becomes maintained constantly at the operating voltage even though the external power supply voltage is increased. This prevents bit lines from becoming charged more than a required level owing to an external power supply voltage variation, so that signal swing width on each bit line and a write recovery time becomes maintained constantly. As a result, there is few or no power consumption in association with an external power supply voltage variation.

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Gyeonggi-do, South Korea

In-Cheol Shin