Hannstar Display Corporation

In-Cha Hsieh

Chih-Yu Peng

Yu-Fang Wang

Chia-Sheng Ho

Shih-Ming Chen

A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.

CMOS process for double vertical channel thin film transistor

A method for manufacturing an LCD panel comprises the steps of providing a substrate having a conducting layer forming a pad and a conducting line, and an isolation layer on the pad and the conducting line, forming a planarization layer on the isolation layer above the conducting line, and a first through hole in the planarization layer, the first through hole exposing the isolation layer and aligned with the conducting line, forming a masking layer on the isolation layer above the pad, and a second through hole in the masking layer, the second through hole exposing the isolation layer and aligned with the pad, and etching the isolation layer with the masking of the planarization layer and the masking layer, whereby the isolation layer exposed by the first and second through hole is removed.

Method for manufacturing an LCD panel

A process for forming a thin film transistor includes steps of (a) forming a gate on a portion of a substrate, (b) forming a gate dielectric layer, a semiconductor layer, a source, a drain, and a passivation in order on the substrate, and (c) proceeding a thermal treatment under atmosphere of a specific assistant gas. The specific assistant gas is one selected from a group consisting of hydrogen, steam, inert gases, and gas mixtures thereof. After providing the specific assistant gas during the thermal treatment, the process can improve the output property of the thin film transistor for avoiding double hump phenomenon.

Thermal treatment process for forming thin film transistors without the use of plasma treatment to further improve the output property of the thin film transistor

A method of patterning an indium tin oxide (ITO) layer is performed on a glass substrate. First, using sputtering, an amorphous ITO layer is deposited on the glass substrate. Then, using excimer laser annealing (ELA), the amorphous ITO layer within a predetermined pattern is turned into a crystalline ITO layer. Finally, using an etch solution, the amorphous ITO layer outside the predetermine pattern is removed.

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Hsinchu Hsien, Taiwan

In-Cha Hsieh