Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Other

Amkor Technology Korea, Inc.

In Bae Park

Jong Sik Paek

Won Chul Do

Byong Jin Kim

Choon Heung Lee

Sung Kyu Kim

Seong Min Seo

Sang Won Kim

Sang Gyu Lee

Eun Sook Sohn

Boo Yang Jung

Glenn A Rinne

Do Hyung Kim

Doo Hyun Park

Ji Young Chung

Jae Min Bae

No Sun Park

Yong Min Song

Hyung Il Jeon

Pil Je Sung

Jin Hee Park

Chang Min Lee

Jin Seong Kim

Yi Seul Han

Kwang Seok Oh

Sung Geun Kang

Chang Deok Lee

Jae Beum Shim

SungGeun Kang

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Wafer level fan out semiconductor device and manufacturing method thereof

A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.

Semiconductor device and manufacturing method thereof

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Semiconductor package and method therefor

The present invention relates generally to a handpiece laser treatment apparatus for treating an affected area by irradiating lasers thereto. More particularly, the present invention relates to a handpiece laser treatment apparatus capable of adjusting the drawn length of an optical fiber in which laser is irradiated. The handpiece laser treatment apparatus capable of adjusting the length of optical fiber according to the present invention comprises: a laser module for generating a laser; an optical fiber that is connected to the laser module so that the laser is irradiated to the outside; a main body in which the laser module is inserted and disposed in the inside and the optical fiber is projected forwardly; and a slider for adjusting the length of the optical fiber which is projected in front of the body.

Handpiece laser treatment apparatus capable of adjusting length of optical fiber

A method of manufacturing a semiconductor device that can be transferred to a circuit board with improved product reliability, and a semiconductor device manufactured according to the method, are described. A non-limiting example of the manufacturing method includes preparing a wafer having multiple semiconductor die portions formed on the semiconductor wafer, performing a sawing operation to separate the multiple semiconductor die portions into multiple discrete semiconductor die, arranging the multiple discrete semiconductor die on an adhesive member, encapsulating the multiple semiconductor die using an encapsulant, and performing a second sawing operation upon the encapsulated multiple semiconductor die to produce multiple individual encapsulated semiconductor devices.

Manufacturing method of semiconductor device and semiconductor device manufactured thereby

A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.

Semiconductor device utilizing redistribution layers to couple stacked die

A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

Semiconductor device utilzing redistribution layers to couple stacked die

A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.

Stackable wafer level package and fabricating method thereof

A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.

Wafer-level chip-scale package

Growing community of inventors

Seoul, South Korea

In Bae Park