Via Technologies, Inc.

Imran Qureshi

James R Lundberg

Raymond A Bertram

A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.

Scannable fast dynamic register

A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency.

Fast dynamic register with transparent latch

A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.

Fast dynamic register

A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.

P-domino register with accelerated non-charge path

An N-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-charges a pre-charged node high when the symmetric clock signal is low and opens an evaluation window when the pulsed clock signal goes high, and pulls the pre-charged node low if it evaluates, and keeps the pre-charged node high if it fails to evaluate. The output stage provides an output signal based on states of the pre-charged node and a second preliminary output node.

N-domino register with accelerated non-discharge path

A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The evaluation devices are responsive to a clock signal and provide a pre-charged node and an evaluation node. The delayed inversion logic outputs a complete signal that is a delayed and inverted version of the clock signal. The dynamic evaluator, coupled between the pre-charged and evaluation nodes, evaluates a logic function based on a data signal during an evaluation period between operative edges of the clock and complete signals. The latching logic enables the state of an output node to be determined by the state of the pre-charged node during the evaluation period and otherwise clamps the pre-charged node to prevent perturbations of the data signal from propagating to the output node.

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Austin, TX, United States of America

Imran Qureshi