First Solar, Inc.

Spansion Llc.

Advanced Micro Devices Corporation

Cypress Semiconductor Corporation

Imran Khan

Dong-Hyuk Ju

Jun Kang

Shibly S Ahmed

Chuan Lin

Markus Gloeckler

Thomas Truman

Stephen P Murphy

Jianshi Wang

Scott Jacoby

Richard M Fastow

Yue-Song He

Yacov Elgar

Pratima V Addepalli

Gregory A Ritz

Jigish Trivedi

Hsiao-Han Thio

James Ernest Hinkle

Weston Gerwin

Scott Edmonson

San Yu

Dhruv Gajaria

Anthony Maher

Veluchamy Palaniappagounder

Hagop A Nazarian

Zhigang Wang

Modesto Sanchez

Chieu-Yin Chia

Ahmed Shibly

Michael Sweet

A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.

Photovoltaic device including a back contact and method of manufacturing

A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

Controlling the latchup effect

An apparatus and a method for testing and/or conditioning photovoltaic modules. The apparatus includes a set of contacts for contacting electrical conductors of the module and a testing and/or conditioning system for testing and/or conditioning of the module and measuring parameters associated therewith.

Method and apparatus for electrically accessing photovoltaic modules

A system and method for applying an electrical bias to a photovoltaic device in a temperature control chamber, in which the temperature of the photovoltaic device is controlled according to a temperature profile. The temperature profile may include at least one hot phase and at least one cool phase.

System and method for photovoltaic device temperature control while conditioning a photovoltaic device

Characteristics of partially assembled photovoltaic modules can be determined using electrical connection apparatuses and methods. By providing deformable electrical contacts against a partially assembled module on an assembly line, an electrical bias can be applied to the module before the module is completely assembled. An electrical connection apparatus for a photovoltaic module may include a first contact configured to engage a first lead on the photovoltaic module, a second contact configured to engage a second lead on the photovoltaic module, and an electrical power source configured to apply an electrical bias between the first contact and the second contact.

In-process electrical connector

A apparatus and method for manufacturing a photovoltaic module includes components for heating the module and applying an electrical bias to the module to improve photovoltaic module performance and manufacture multiple photovoltaic modules with similar performance.

Electrical bias methods and apparatus for photovoltaic device manufacture

A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.

Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Junction leakage suppression in memory devices

A method for manufacturing a photovoltaic module including a laminating step.

Photovoltaic module manufacture

A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.

Method and apparatus for performing semiconductor memory operations

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Perrysburg, OH, United States of America

Imran Khan