Intermolecular, Inc.

Kabushiki Kaisha Toshiba

Sandisk 3d LLC

Applied Materials, Inc.

Elpida Memory, Inc.

Other

Apple Inc.

Advanced Micro Devices Corporation

Intermoecular, Inc.

Imran Hashim

Tony P Chiang

Yun Yu Wang

Vidyut Gopal

Sandra Guy Malhotra

Takeshi Yamaguchi

Tim Minvielle

Barry Lee Chin

Dipankar Pramanik

Sunil Shanker

Prashant B Phatak

Peijun Ding

Hanhong Chen

Hieu T Pham

Edward L Haywood

Pragati Kumar

Hong Sheng Yang

Bingxi Sun

Randall Higuchi

Mihir Tendulkar

Kurt H Weiner

Xiangxin Rui

Ronald John Kuse

Ryan C Clarke

Nobi Fuchigami

Indranil De

Venkat Ananthan

Jinhong Tong

Gaurav Verma

Zhendong Hong

Monica Sawkar Mathur

Nobumichi Fuchigami

John C Forster

Kapil Vinod Sakariya

Mitsuhiro Horikawa

Nan Lu

Yoram Schwarz

David Chi

Guarav Verma

Vaibhav D Patel

Tony Chiag

Hong-Mei Zhang

Andreas Bibl

Xia Li

Takeshi Nogami

Yezdi N Dordi

Robin W Cheung

John A Higginson

Christy Mei-Chu Woo

Hsin-Hua Hu

Ashok K Sinha

Thomas B Brezoczky

Howard H Tang

Dirk Dewar Brown

Robert A Huertas

Liang Light Chen

Tore Nauta

Daniel A Carl

Susan H Chen

Kenichi Koyanagi

Albert Sanghyup Lee

Richard Hong

Peter W Hey

Thomas Charisoulis

Young-Chang Joo

Sesh Ramaswami

Naonori Fujiwara

Ralph E Kauffman

Seh-Kwang Lee

Hybrid chiplets, display backplanes, and displays with integrated hybrid chiplets are described. In an embodiment, a hybrid chiplet includes a micro LED chiplet stacked on a micro driver chiplet that includes at least one drive transistor and a bottom side including a plurality of bottom chiplet contacts for electrical connection with a display backplane.

Stacked hybrid micro LED pixel architecture

Display integration schemes are described for passivating LEDs and providing conductive terminal connections. In accordance with embodiments, a sidewall passivation layer is formed around the LEDs. The sidewall passivation layer may or may not be contained within a well structure. A top electrode layer is formed to electrically connect the LEDs to conductive terminal routing.

Backplane LED integration and functionalization structures

Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Method for forming a doped metal oxide for use in resistive switching memory elements

Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Embedded nonvolatile memory elements having resistive switching characteristics

Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks

Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes.

High productivity combinatorial workflow to screen and design chalcogenide materials as non volatile memory current selector

Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., 'set' and 'reset' steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

Nonvolatile memory device having a current limiting element

Embodiments of the invention include a method of forming a nonvolatile memory device that contains a resistive switching memory element with improved device switching performance and lifetime, due to the addition of a current limiting component. In one embodiment, the current limiting component comprises a resistive material configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel oxide layer that is a current limiting material and an oxygen barrier layer that is an oxygen deficient material disposed within a resistive switching memory element in a nonvolatile resistive switching memory device.

Nonvolatile memory device using a tunnel oxide layer and oxygen blocking layer as a current limiter element

A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

DRAM MIM capacitor using non-noble electrodes

Designs and programming schemes can be used to form memory arrays having low power, high density and good data retention. High resistance interconnect lines can be used to partition the memory array can be partitioned into areas of high data retention and areas of low data retention. Variable gate voltages can be used in control transistors to store memory values having different data retention characteristics.

Memory arrays for both good data retention and low power operation

Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Atomic layer deposition of metal oxides for memory applications

Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.

Diffusion barrier layer for resistive random access memory cells

Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Nonvolatile memory device having an electrode interface coupling region

MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.

Method of forming an asymmetric MIMCAP or a Schottky device as a selector element for a cross-bar memory array

A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (&#x3c;30% crystalline) after an anneal step. The high band gap material will remain amorphous (&#x3c;30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (&#x2267;30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack.

Methods to improve electrical performance of ZrO2 based high-K dielectric materials for DRAM applications

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Saratoga, CA, United States of America

Imran Hashim