Advanced Micro Devices Corporation

Legerity, Inc.

Imran Baqai

Michael A Nix

Merle L Miller

Jeffrey Jay Anderson

A communications system includes a communications channel, a first processing unit; and interface unit, and an interrupt controller. The first processing unit is adapted to monitor the communications channel and provide a plurality of status bits. The interface unit includes an interrupt register. The interrupt controller is adapted to identify a plurality of interrupts in response to changes in the status bits. Each interrupt has a priority, and the interrupt controller is adapted to store selected interrupts in the interrupt register in an order determined by the priority of the interrupts. A method includes monitoring a communications channel. A plurality of status bits associated with the monitoring are provided. A plurality of interrupts are identified based on changes in the status bits, each interrupt having a priority. Selected interrupts are stored in an interrupt queue in an order determined by the priority of the interrupts.

Method and apparatus for prioritizing interrupts in a communication system

An extended chip select reset circuit to generate a reset signal for a device, such as a SLAC, using the chip select line. When the chip select line has been maintained in an active state for at least a predetermined amount of time corresponding to a plurality of data clocks, then a reset signal is generated in order to reset the device. The plurality of data clocks is more than a number of data clocks used to clock in a word of data to the device in a normal mode of operation.

Extended chip select reset apparatus and method

An apparatus for counting occurrences of a particular input during a plurality of succeeding periods. The apparatus comprises an input terminal for receiving the input, a toggle signal generating circuit for generating a periodic toggle signal to mark the plurality of periods, and a plurality of n counter cell circuits for effecting the counting in n bits. Each counter cell circuit generates at least a respective bit output, a respective toggle output, and respective carry output. The counter cell circuits are arranged in hierarchical order from a least-significant counter cell circuit to a most-significant counter cell circuit. Each of the respective counter cell circuits is coupled with the next-most-significant counter cell circuit and provides the respective toggle output to the next-most-significant counter cell circuit as a respective toggle input, provides the respective carry/output to the next most-significant counter cell circuit as the respective carry input, except the most-significant counter cell circuit n receives its respective toggle input from the respective carry output of the twice-less-significant counter cell circuit cell circuit n-2.

Growing community of inventors

Austin, TX, United States of America

Imran Baqai