Via Technologies, Inc.

Iming Pai

Xinwei Yang

Jinming Gu

Yi-Fang Michael Shiuan

The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on multiple display devices of a computer that contains a system memory directly accessed by the computer's CPU during the CPU's power saving non-responding period, wherein there is provided sufficient system bandwidth, the mechanism of the present invention is independent on the resolution running on each display device and the number of display devices connected to the computer system. The mechanism provides two approaches to achieve continuous display of image/graphics data on multiple display devices computer system. In the first approach, a common clock source is used to coordinate display device horizontal synchronization signals, vertical synchronization signals, horizontal blank periods, and vertical blank periods. In the second approach, the mechanism has a control on the lengths and occurrences of the display device blank periods.

Continuous graphics display method for multiple display devices during the processor non-responding period

An interface unit is described that comprises a buffer for storing captured video data generated by a three dimensional (3D) device intended for a 3D monitor. The interface unit further comprises a synchronization signal extractor configured to extract vertical synchronization (vsync) signals from the video data and a control signal unit configured to derive control signals for a viewing device based on the stored vsync signals. The interface unit transmits the control signals to the viewing device.

Systems and methods for controlling a three dimensional (3D) compatible viewing device

The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on dual display devices of a computer that contains a Display FIFO and a system memory directly accessed by the computer's CPU, wherein at least one of the display devices is running in a low-resolution mode, the mechanism comprising: determining which of the display devices is running in the low-resolution mode; receiving a power saving signal from the CPU; requesting an access to the system memory, and pre-storing the image/graphics data for the low-resolution device into the Display FIFO; and triggering the CPU power saving process according to a display timing scheme of the other display device.

Continuous graphics display for dual display devices during the processor non-responding period

A mechanism is disclosed for adjusting one or more operational parameters of a component in such a way that the adjustment has minimal impact on graphics display. When a component (e.g. a processor) wishes to adjust one or more of its operational parameters (e.g. operating clock frequency), it submits a request to a graphics processing mechanism (GPM). In response, the GPM, which controls multiple displays, sends a response to the component at a proper time to cause the component to adjust the operational parameter during a time period in which a first display and a second display are both experiencing a blank period. By coordinating the timing of the adjustment in this way, it is possible to keep the size of a video memory to a minimum.

Mechanism for adjusting the operational parameters of a component with minimal impact on graphics display

An uninterrupted data display method for a computer system having a system memory directly accessed by a processor, for preventing disrupted data display from transmission break is disclosed. The method is accomplished before the processor goes into a non-responding period due to an execution of an economical process. The method includes the steps of: (i) providing a data storage device having a depth for storing a period long of data. (ii) Comparing the period of said depth to the non-responding period, if the period of said depth is longer than the non-responding period, jump to step (iii), otherwise, to step (iv). (iii) Loading the period long of data from a system memory into the data storage device then jump to step (v). (iv) Detecting a synchronization pulse then jump to step (v), wherein step (v) is to be accomplished within a non-display period, and, (v) executing the economical process.

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San Jose, CA, United States of America

Iming Pai