Taiwan Semiconductor Manufacturing Comp. Ltd.

Iman Hsu

Yuan-Chang Huang

Chin-Kun Wang

A method is provided wherein a process suitable for subtractive etching of titanium nitride layers useful in the fabrication of semiconductor integrated circuit devices can be efficiently employed on commercially-available plasma reactor system equipment normally suitable only for subtractive etching of passivation layer materials and the like, resulting in increased efficiency and reduced cost in the manufacturing of such devices.

Method for etching titanium nitride layers

A planarization process, featuring removal of spin on glass, used to fill narrow spaces between metal lines, has been developed. A dual dielectric, of underlying silicon oxide, and overlying silicon nitride, are initially used to passivate the metal lines, followed by the spin on glass fill. A RIE etchback of the spin on glass proceeds to a point in which the silicon nitride, on the metal line, is exposed. The exposed silicon nitride is then removed leaving a silicon oxide passivated metal line, and seamless insulator filled spaces. The ability of not exposing the passivating silicon oxide to RIE echback process, allows seamless fills to result.

Optimized planarization process for SOG filled vias

This invention provides a method of forming a bowled contact or via hole in a boron and phosphorous doped tetraethyl orthosilicate, BPTEOS, dielectric film which will provide superior edge coverage when filled with metal. The bowled contact or via hole has an edge profile with a small entry angle, the angle between the surface of the dielectric film and the line tangent to the contact or via hole edge profile. The method of this invention uses a 10:1 Buffered Oxide Etch, BOE, to remove the densified region on the surface of the BPTEOS film. The contact or via hole is then formed using isotropic etching followed by a vertical anisotropic etch.

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Miao Li, Taiwan

Iman Hsu