Winbond Electronics Corporation

Windbond Electronics Corp.

Im-Cheol Ha

Jun-Lin Yeh

Chung-Meng Huang

Shang-Wen Chang

Jen-Fu Su

A non-volatile memory apparatus and a refresh method thereof are provided. A control circuit determines whether threshold voltages of memory cells in a memory sectors are larger than a refresh read reference voltage and smaller than a refresh program verify reference voltage, and the control circuit determines that a memory cell needs refreshing if the threshold voltage of the memory cell is larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage.

Nonvolatile memory apparatus and refresh method thereof

This invention introduces a flash memory device and a method which are capable of quickly recovering the over-erased memory cells while preventing adverse influence to normal cells that are not over-erased. The flash memory device comprises a memory array and a memory controller coupled to the memory array. The memory controller is configured to select a memory block which comprises at least one over-erased memory cell. The memory controller is further configured to apply a negative voltage to the common bulk line and the common source line of the selected memory block. The memory controller is further configured apply a positive voltage to word lines that are coupled to the at least one over-erased memory cell in the selected memory block, and apply the positive voltage to word lines that are not coupled to any one of the at least one over-erased memory cell in the selected memory block.

Flash memory device and method for recovering over-erased memory cells

A memory cell structure is provided. A first doping region is formed in a substrate. A second doping region is formed in the substrate. A first gate is formed on the substrate. The first and second doping regions and the first gate constitute a first transistor. A first word line is electrically connected to the first gate. The first word line firstly extends along a first direction and then along a second direction which is different from the first direction. A resistive layer is electrically connected to the first doping region. A conductive layer comprises a first source line and a bit line. The first source line is electrically connected to the second doping region, and the bit line is electrically connected to the resistive layer. The first and second doping regions extend along a third direction which is different from the first and second directions.

Memory cell structure and formation method thereof

A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors and a plurality of odd pass transistors. Each of the even pass transistors has a, control terminal coupled to a respective one of a plurality of even selection lines, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to an even global bit line. Each of the odd pass transistors has a control terminal coupled to a respective one of a plurality of odd selection lines, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to an odd global bit line.

Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells

A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors, a plurality of even clamp transistors, a plurality of odd pass transistors, and a plurality of odd clamp transistors. Each of the even clamp transistors has a control terminal coupled to an even clamp line, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to a ground voltage. Each of the odd clamp transistors has a control terminal coupled to an odd clamp line, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to the ground voltage.

Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns which do not pass the over-erased column verification test. For the columns processed by the over-erased column repair process but still incapable of passing the over-erased column verification test, an over-erased bit verification test is performed on each bit thereof. The bits incapable of passing the over-erased bit verification test are further processed by an over-erased repair process individually.

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Hsinchu, Taiwan

Im-Cheol Ha