Intel Corporation

Samsung Electronics Co., Ltd.

Ilya Osadchiy

Boris Ginzburg

Ronny Ronen

Yoav Zach

Esfirush Natanzon

Efraim Rotem

Eliezer Weissmann

Alon Naveh

Dheeraj R Subbareddy

Eugene Gorbatov

David A Koufaty

Michael Mishaeli

Anil Aggarwal

Robert L Farrell

Aamer Jaleel

Scott D Hahn

Paolo L Narvaez

Yuval Yosef

Esfir Natanzon

Tong Li

Hisham Abu-Salah

Doron Sabo

Kenzo Van Craeynest

Avi Mendleson

Learning-based color correction (e.g., auto while balance (AWB)) procedures may be trained based on datasets from different sensors using a pre-processing procedure. Each input pixel may be converted into a sensor-independent representation through multiplication by a sensor-specific color conversion function (e.g., a 3&#xd7;3 matrix). The sensor-specific color conversion function may be obtained based on a sensor type. For example, the sensor-specific color conversion function, such as a 3&#xd7;3 matrix, may be obtained by a corresponding sensor calibration procedure performed using laboratory images of a color checker chart subject to standard illuminants. Parameters of the sensor-specific color conversion function may be optimized in a chromaticity space. For instance, a sensor-specific 3&#xd7;3 matrix for color conversion may be optimized using a distance in the chromaticity space between calibration data (e.g., calibration configurations) and sensor-independent targets (e.g., a target sensor-independent representation for each calibration configuration).

Data pre-processing for cross sensor automatic white balance

A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Aggregated page fault signaling and handling

Aggregated page fault signaling and handline

A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

CPU/GPU synchronization mechanism

In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

Providing an asymmetric multicore processor system transparently to an operating system

Growing community of inventors

Haifa, Israel

Ilya Osadchiy