International Business Machines Corporation

Apple Inc.

Ilya Granovsky

Khary J Alexander

Giora Biran

Etai Adar

Christian Jacobi

Avraham Ayzenfeld

Tom Greenshtein

Emmanuel Elder

Doron Rajwan

Gregory William Alexander

Lior Zimet

James R Mitchell

Gregory Miaskovsky

Alexander Gendler

Elchanan Perlin

Sandeep Kumar Gupta

Zorik Machulsky

Jonathan T Hsieh

Sergio Kolor

Tal Kuzi

Shaul Yohai Yifrach

Michael Bar-Joshua

Daniel U Becker

Vivek Venkatraman

Nir Leshem

Paul Joseph Mattos

Boaz Yeger

Or Davidi

Amanvir Singh Sidana

Idan Mondjak Kedem

Saher Odeh

Elli Bagelman

Oren Bar

Itay Poleg

Efrat Greenberg

A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.

Cache writeback circuit

Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

Quality-of-service-based fabric power management

An apparatus includes a plurality of coherent agents, and a coherence directory that includes directory ways for storing coherency information. The coherence directory may be configured to determine that a cache block that is not currently cached among the coherent agents, is stored in a first coherent agent. The coherence directory may be further configured to, in response to this determination, create a particular entry in a selected one of the directory ways. The coherence directory may also be configured to send, to the first coherent agent, an indicator identifying a directory way that includes the entry. In response to a second coherent agent caching the cache block, the coherence directory may update the entry to include the second coherent agent. The first and second coherent agents may be configured to receive copies of the indicator, and to store their copy in locations associated with the cache block.

Coherence directory way tracking in coherent agents

Techniques are disclosed relating to data rate limiting based on toggle rate. In some embodiments, toggle detector circuitry determines a toggle rate between consecutive clock cycles for node circuitry that communicates via a data bus and provides toggle information to data rate limiter circuitry based on the determined toggle rate. The data rate limiter circuitry may limit data rate based on toggle information and the one or more limit inputs. Toggle detector circuitry may be configured to aggregate the toggle rate over multiple cycles using a rolling multi-cycle window, generate toggle information for windows of different lengths, generate toggle information for different data, or some combination thereof.

Toggle-based power management

An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

Memory cache with partial cache line valid states

A memory controller with a separate transaction table for real-time transactions is disclosed. A system includes a plurality of agents and a memory controller configured to receive real-time and non-real-time memory requests from ones of the plurality of agents. The memory controller includes a real-time incoming transaction table configured to store those memory requests received from a subset of the plurality of agents that are real-time memory requests, and a non-real-time incoming transaction table configured to store those memory requests received from the subset of the plurality of agents that are non-real-time memory requests. The memory controller further includes an arbitration circuit configured to select a memory request from among memory requests stored in the real-time and non-real-time incoming transaction tables and further configured to enforce a quality of service policy for the real-time memory requests.

Memory controller with separate transaction table for real time transactions

Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.

Multi-die power management in SoCs

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.

Programmed input/output message control circuit

A queue management capability enables allocation and management of tracking queue entries, such as load and/or store queue entries, at execution time. By introducing execution-time allocation of load/store queue entries, the allocation point of those entries is delayed further into the execution stage of the instruction pipeline, reducing the overall time the entry remains allocated to a specific instruction. The queue management capability may also resolve deadlock conditions resulting from execution-time allocation of the queue entries and/or provide a mechanism to avoid such deadlock conditions.

Delayed allocation of an out-of-order queue entry and based on determining that the entry is unavailable, enable deadlock avoidance involving reserving one or more entries in the queue, and disabling deadlock avoidance based on expiration of a predetermined amount of time

An apparatus and method of submitting hardware accelerator engine commands over an interconnect link such as a PCI Express (PCIe) link. In one embodiment, the mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting a remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs a co-processor request completion sequence (status update, write to flag, interrupt) included in the co-processor command.

Methods for the submission of accelerator commands and corresponding command structures to remote hardware accelerator engines over an interconnect link

Techniques for generating a design structure for cache power reduction are described herein. In one example, a system includes logic to detect memory address information corresponding to accessed data in a first instruction, and detect memory address information corresponding to accessed data in a second instruction. The logic can also compare the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detect, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. The logic can also execute the second instruction using the accessed data from the first instruction.

Structure for reducing power consumption for memory device

A method in a computer-aided design system for generating a functional design model of a processor, is described herein. The method comprises detecting memory address information corresponding to accessed data in a first instruction, and detecting memory address information corresponding to accessed data in a second instruction. The method further comprises comparing the memory address information corresponding to the first instruction and the memory address information corresponding to the second instruction, and detecting, based on the comparison, that the accessed data in the first instruction and the accessed data in the second instruction are in a same data range of the memory device. In addition the method comprise executing the second instruction using the accessed data from the first instruction and detecting an error from the execution of the second instruction.

Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is issued into an instruction pipeline, the load queue entry comprising a valid tag that is set and a keep tag that is unset. Another aspect includes based on the flushing of the load instruction, unsetting the valid tag and setting the keep tag. Another aspect includes reissuing the load instruction into the instruction pipeline. Another aspect includes based on determining that the allocated load queue entry corresponds to the reissued load instruction, setting the valid tag and leaving the keep tag set. Another aspect includes based on completing the reissued load instruction, and based on the valid tag and the keep tag being set, updating the OSC history table corresponding to the load instruction.

Growing community of inventors

Haifa, Israel

Ilya Granovsky