Samsung Electronics Co., Ltd.

Ill Heung Choi

Young Hee Song

A method of manufacturing a semiconductor package, including: preparing a first semiconductor chip, where a plurality of first central electrode pads are formed along a center of an active surface of the first semiconductor chip, preparing a second semiconductor chip, where a plurality of second central electrode pads are formed along a center region of an active surface of the second semiconductor chip, and a plurality of edge electrode pads are formed along an edge of the second semiconductor chip, attaching the second semiconductor chip to a substrate, connecting electrically the edge electrode pads of the second semiconductor chip to the substrate, encapsulating the connection between the edge electrode pads and the substrate, forming a plurality of metal bumps on the central electrode pads of the second semiconductor chip, and stacking the first semiconductor chip on the second semiconductor chip so that the first central electrode pads of the first semiconductor chip attach to the respective second central electrode pads of the second semiconductor chip via the metal bumps.

Semiconductor package with semiconductor chips stacked therein and method of making the package

An improved dual die package is disclosed. The dual die package includes a first lead frame connected to a first semiconductor chip and a second lead frame connected to a second semiconductor chip. The first leads and the second leads are electrically connected to one another using a wirebonding process rather than a thermocompression process thereby allowing conventional packaging equipment to be used when manufacturing a dual die package.

Duel die package

A method for manufacturing a semiconductor chip package includes: preparing a semiconductor chip having center and edge bonding pads and a substrate, which includes a first window, a second window, connection pads, external terminal pads, and a wiring pattern; attaching the semiconductor chip on the substrate such that the first window exposes the center bonding pads and the second window exposes the edge bonding pads; connecting the first and second bonding pads to corresponding connection pads; encapsulating side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads; and forming external terminals on the external terminal pads of the substrate. The encapsulating includes a first encapsulation of the side surfaces of the semiconductor chip and a portion of the bottom surface of the substrate and a second encapsulation of the bonding wires and the connection pads.

Semiconductor chip package having a semiconductor chip with center and edge bonding pads and manufacturing method thereof

A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a substrate, and metal bumps. The first semiconductor chip has first central electrode pads along a center of the first semiconductor chip. The second semiconductor chip has second central electrode pads along a center of the second semiconductor chip and edge electrode pads along an edge of the second semiconductor chip. The metal bumps connect the first central electrode pads of the first semiconductor chip to the second central electrode pads of the second semiconductor chip. The second semiconductor chip is mounted on the substrate, and the edge electrode pads of the second semiconductor chip are electrically connected to the substrate. A method of manufacturing a semiconductor package includes: preparing the first and second semiconductor chips; attaching the second semiconductor chip to a substrate; connecting electrically the edge electrode pads of the second semiconductor chip to the substrate; encapsulating the connection between the edge electrode pads and the substrate; forming metal bumps on the central electrode pads of the second semiconductor chip; and stacking the first semiconductor chip on the second semiconductor chip so that the first central electrode pads of the first semiconductor chip attach to the respective second central electrode pads of the second semiconductor chip via the metal bumps.

A semiconductor chip package includes a semiconductor chip and a substrate on which the semiconductor chip attaches. The semiconductor chip includes center and edge bonding pads. The substrate includes a first window that exposes the center bonding pads, a second window that exposes the edge bonding pads, connection pads around the first and second windows, external terminal pads, and a wiring pattern. The semiconductor chip package further includes bonding wires, an encapsulation body, and external terminals. The bonding wires connect the center and edge bonding pads of the semiconductor chip to the connection pads of the substrate. A method for manufacturing a semiconductor chip package includes: preparing a semiconductor chip having center and edge bonding pads and a substrate, which includes a first window, a second window, connection pads, external terminal pads, and a wiring pattern; attaching the semiconductor chip on the substrate such that the first window exposes the center bonding pads and the second window exposes the edge bonding pads; connecting the first and second bonding pads to corresponding connection pads; encapsulating side surfaces of the semiconductor chip, a portion of the bottom surface of the substrate, the bonding wires, and the connection pads; and forming external terminals on the external terminal pads of the substrate. The encapsulating includes a first encapsulation of the side surfaces of the semiconductor chip and a portion of the bottom surface of the substrate and a second encapsulation of the bonding wires and the connection pads.

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Cheonan, South Korea

Ill Heung Choi