Alcatel Lucent

Alcatel-lucent USA Inc.

Lucent Technologies Inc.

Nokia Technologies Oy

Ilija Hadzic

Dusan Suvakovic

Martin D Carroll

Dennis Raymond Morgan

Doutje T Van Veen

Edward Stanley Szurkowski

Glenn M Boles

Peter Johannes Winzer

Krishan Kumar Sabnani

Theodore Sizer

Katherine Hua Guo

Zulfiquar Sayeed

Hungkei Keith Chow

Alfred E Dunlop

Ronald L Sharp

Alf Neustadt

Manyalibo Joseph Matthews

Andrew Adamiecki

Hans C Woithe

Lou Salaun

Sara Ayoubi

Andrew Larry Adamiecki

An apparatus in one embodiment comprises a client device configured to communicate with a remote system over a network. The client device comprises a processor, a memory, an input device and a display. The client device is configured to detect an input event generated at the input device, to store in the memory a local time associated with the input event, and to transmit information characterizing the input event to the remote system over the network. The client device is configured to receive from the remote system a video signal comprising an event index of the input event. An event index is extracted from the video signal, and a round-trip latency is computed between the input event and a corresponding video output of the client device based at least in part on a local time associated with the extracted event index and the stored local time associated with the input event.

Video-based measurement of round-trip latency from user input event to corresponding video output

A proxy mixer includes a transceiver configured to receive one or more first requests to provide one or more first media streams to one or more first endpoints. The one or more first media streams are generated by one or more second endpoints. The one or more first requests indicate one or more first quality metrics for the one or more first media streams. The transceiver is also configured to provide one or more second requests for the one or more second endpoints to generate the one or more first media streams at an aggregate quality metric that equals a highest quality metric of the one or more first quality metrics. The transceiver is further configured to transmit the one or more first media streams towards the one or more first endpoints.

Scalable architecture for media mixing

A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.

Central office based virtual personal computer

An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery module further comprises a discontinuity detector configured to detect a delay discontinuity in timing messages received in the slave device from the master device, and a loop controller operative to place the clock recovery loop in a particular state responsive to the detected discontinuity. The particular state comprises a state in which a normal operating mode of the loop is interrupted and a compensating drive signal is applied to a clock source of the slave device to at least partially offset phase error accumulation associated with the detected discontinuity.

Frequency synchronization with compensation of phase error accumulation responsive to a detected discontinuity

In a dual speed passive optical network, an optical line termination (OLT) transmits a communication signal having a 10-Gb/s partition and a 2.5-Gb/s partition. The 10-Gb/s partition includes a 10 G data signal and a 2.5 G clock signal so that the PLL of a 2.5 G (legacy) optical network termination (ONT) can remain locked while a 10 G ONT is receiving data. The 2.5 G clock signal includes 1-bit spike signals of greater amplitude than the 10 G data signal.

System and method for dual speed passive optical networks

An endpoint or other communication device of a communication system includes a clock recovery loop having a phase error estimator. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery loop is configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device. The phase error estimator comprises a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop.

Frequency synchronization using clock recovery loop with adaptive packet filtering

A transparent clock adaptor is provided for use with a router, switch or other network device that does not otherwise support transparent clock functionality. The transparent clock adaptor comprises a network port for coupling to a link of a network, a local port for coupling to a port of the network device, transparent clock processing circuitry operative to perform one or more transparent clock timing adjustment operations for each of a plurality of packets including at least one packet arriving in the adaptor via the network port and at least one packet arriving in the adaptor via the local port, and a synchronization interface for communicating with a corresponding synchronization interface of at least one other transparent clock adaptor. The adaptor can operate both as an ingress adaptor for packets arriving over the network link for delivery to the network device and as an egress adaptor for packets arriving from the network device for delivery over the network link.

Transparent clock adaptor for a network device

An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop utilizes a frequency error estimator implemented as a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps, and a loop filter implemented as a series combination of an adaptive-bandwidth filter and a proportional-integral controller. The clock recovery module may further comprise a discontinuity detector configured to detect a discontinuity in delays of respective timing messages, and a loop controller operative to place the clock recovery loop in a particular state responsive to detection of the discontinuity.

Method, apparatus and system for frequency synchronization between devices communicating over a packet network

An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.

Frequency synchronization using first and second frequency error estimators

An apparatus for enhancing packet communication is disclosed. In one embodiment, the apparatus includes an encoder configured to convert input data to a binary coded base system of an augmented code employing a base of an original code used for coding the input data, wherein the augmented code employs more symbols for coding than the original code, the encoder including: (1) an adder configured to add the input data to a multiplication product to generate a base sum that is binary-coded in the augmented code, (2) a multiplier configured to multiply an accumulated value by a base of the original code to provide the multiplication product that is binary-coded in the augmented code, and (3) an accumulator configured to employ the base sum to provide an accumulated value as an output for the encoder, wherein the accumulated value is binary-coded in the augmented code to represent the input data.

Apparatus for enhancing packet communication

A communication device comprises a receiver and a data recovery module. The receiver may be an element of a serial transceiver embedded in or otherwise associated with an FPGA or other type of reconfigurable hardware. The receiver is operable with an unlocked sampling clock. The data recovery module is configured to detect transition edges in data signal samples generated by the receiver using the unlocked sampling clock, and to determine from the detected edges a sampling point for use in recovery of the associated data. The data recovery module is further configured to provide adjustment in the sampling point in the presence of transition edge variations, such as one or more exception conditions, that are attributable to the unlocked sampling clock.

High-speed serial transceiver with sub-nominal rate operating mode

A processing device, configured to implement at least a portion of a scheduled medium-access protocol (SMAP) in a communication system, comprises a processor, a memory coupled to the processor, and one or more additional hardware modules. The functionality of the portion of the SMAP implemented in the processing device is partitioned between software, stored in the memory and executable by the processor, and hardware comprising the one or more additional hardware modules. In an illustrative embodiment, the processing device comprises a head-end device of a passive optical network, and the functionality comprises at least a scheduler and a grant generator, with the scheduler being implemented in the software and the grant generator being implemented in the hardware.

Software-hardware partitioning of a scheduled medium-access protocol

Techniques for synchronizing the clock of a local telecommunications network connected to a remote clock source through an asynchronous transport network such as an Ethernet metropolitan area transport network. A basic holdover loop for retaining the current reconstructed clock frequency signal receives weighted corrections from an open loop and a network time protocol filter loop. The open loop measures data packet interarrival times on the local network and calculates a first reconstructed clock frequency signal. The network time protocol loop applies network time protocol to generate timestamps over the asynchronous transport network which are used to generate a second reconstructed clock frequency signal. The first and second reconstructed clock frequency signals are combined using dynamically adjusted weight factors and compared with the current reconstructed clock frequency signal to correct the latter which then synchronizes the clock of the local telecommunications network.

Systems and methods for synchronization in asynchronous transport networks

The problems of large tables in Ethernet switches used on a metropolitan area scale, and the exposure of the enterprise network topologies, can be avoided by encapsulating each original Ethernet packet, which originates in a first network of an entity, e.g., an enterprise, a customer, or a network service provider, within another Ethernet packet which is given a source address that identifies the new encapsulating packet as originating at a port of a switch that is located at the interface between the first network in which the original packet originated and a second Ethernet network, e.g., the metropolitan area Ethernet network, which is to transport the encapsulating packet. When the encapsulating packet would exceed the allowable Ethernet packet length, the original packet may be split up at the interface between the first and second network and the resulting parts encapsulated into two encapsulating packets.

Ethernet packet encapsulation for metropolitan area ethernet networks

A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.

Growing community of inventors

Millington, NJ, United States of America

Ilija Hadzic