Ovics

Apple Inc.

Maxim Integrated Products, Inc.

Geo Semiconductor Inc.

Mips Tech Limited

Ilie Garbacea

Sorin Constantin Cismas

Lulin Chen

José Roberto Alvarez

Guy Cote

Chaohao Wang

Brijesh Tripathi

Joshua P De Cesare

Mahesh B Chappalli

Christopher P Tann

Arthur L Spence

Chengrui Le

Malcolm D Gray

Kristan Jon Monsen

Hopil Bae

Paolo Sacchetto

Zhibing Ge

Kingsuk Brahma

Jie Won Ryu

Marc Albrecht

Sandro Hermann Pintz

Shih-Chyuan Fan Jiang

Lu Zhang

Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

Timestamp based display update mechanism

A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.

Rescheduling threads using different cores in a multithreaded microprocessor having a shared register pool

Systems and methods are provided for improving displayed image quality of an electronic display that includes a display pixel. The electronic display displays a first image frame directly after a second image frame by applying an analog electrical signal to the display pixel. To facilitate display of the first image frame, circuitry receives image data corresponding to the image frame, in which the image data includes a grayscale value that indicates target luminance of the display pixel; determines expected refresh rate of the first image frame based at least in part on actual refresh rate of the second image frame; determines a pixel response correction offset based at least in part on the expected refresh rate of the first image frame; and determines processed image data by applying the pixel response correction offset to the grayscale value, in which the processed image data indicates magnitude of the analog electrical signal.

Step-down pixel response correction systems and methods

Systems and methods for improving displayed image quality of an electronic display including a display pixel that displays an image frame based at least in part on an analog electrical signal supplied to the display pixel are provided. In some embodiments, control circuitry instructs the electronic display to display the image frame based at least in part on an expected charge accumulation in the display pixel determined using a charge accumulation model that describes one or more electric fields expected to be present in the display pixel when displaying the image frame and that provides a display pixel state indicative of expected charge accumulation in the display pixel when the image frame is to be displayed based at least in part on the one or more electric fields.

Display pixel charge accumulation compensation systems and methods

Processor-to-processor (P-P) and/or broadcast proxies may be designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default processor-to-processor or broadcast routing algorithms used by data switches within the matrix to route messages would not deliver the messages to all intended recipients. The broadcast proxies broadcast messages within individual non-overlapping broadcast domains of the matrix. P-to-P and broadcast proxies may be designated as part of a boot-time testing/initialization sequence. Improving system fault tolerance allows improving semiconductor processing yields, which may be of particular significance in relatively large integrated circuits including large numbers of relatively-complex matrix processors.

Matrix processor proxy systems and methods

In some embodiments, macroblock-level encoding parameters are assigned to weighted linear combinations of corresponding content-category-level encoding parameters. For example, a macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics. Content-category-level statistics may be used in encoding subsequent frames.

Video encoding control using non-exclusive content categories

According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substrates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities. A hardware thread profiler including global, run and wait profiler registers is used to monitor thread performance to facilitate software development.

Hardware multithreading systems and methods

In some embodiments, processor-to-processor and/or broadcast proxies are designated in a microprocessor matrix comprising a plurality of mesh-interconnected matrix processors when default processor-to-processor or broadcast routing algorithms used by data switches within the matrix to route messages would not deliver the messages to all intended recipients. The broadcast proxies broadcast messages within individual non-overlapping broadcast domains of the matrix. P-to-P and broadcast proxies may be designated as part of a boot-time testing/initialization sequence. Improving system fault tolerance allows improving semiconductor processing yields, which may be of particular significance in relatively large integrated circuits including large numbers of relatively-complex matrix processors.

In some embodiments, macroblock-level encoding parameters are assigned to weighted Linear combinations of corresponding content-category-level encoding parameters. A macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics. Content-category-level statistics may be used in encoding subsequent frames.

According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data switch including a data switch link register and matrix routing logic. The data switch link register includes one or more matrix link-enable register fields specifying a link enable status (e.g. a message-independent, p-to-p, and/or broadcast link enable status) for each inter-processor matrix link of the processor. The matrix routing logic routes inter-processor messages according to the matrix link-enable register field(s). A particular link may be selected by a current matrix processor by selecting an ordered list of matrix links according to a relationship between &#x394;H and &#x394;V, and choosing the first enabled link in the selected list for routing. &#x394;H is the horizontal matrix position difference between the current (sender) processor and a destination processor, and &#x394;V is the vertical matrix position difference between the current and destination processors.

Matrix processor data switch routing systems and methods

In some embodiments, an integrated circuit comprises a microprocessor matrix including a plurality of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch configured to direct inter-processor communications within the matrix, and a mapping unit configured to generate a data switch functionality map for a plurality of data switches in the microprocessor matrix. The data switch functionality map is generated by sending a first message through the matrix, and, setting a first functionality status designation for the first data switch in the data switch functionality map upon receiving a reply to the first message from a first data switch through the matrix.

Matrix processor initialization systems and methods

In some embodiments, content-category-level encoding statistical indicators (statistics) are assigned to weighted linear combinations of corresponding macroblock-level statistics. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A given macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Macroblock-level encoding parameters are generated by combining content-category-level parameters.

Video encoding statistics extraction using non-exclusive content categories

A method for hybrid video coding is disclosed. The method generally includes the steps of (A) calculating a bit rate based on a percentage of quantized zero coefficients resulting from encoding a plurality of components of a video signal, (B) calculating a distortion based on the percentage of quantized zero coefficients, (C) calculating a plurality of variances of a plurality of prediction error pictures and (D) calculating an adaptive Lagrangian multiplier in a Lagrangian rate-distortion optimization as a function of the bit rate, the distortion and the variance to minimize a Lagrangian cost.

Method and apparatus of adaptive lambda estimation in Lagrangian rate-distortion optimization for video coding

In some embodiments, each matrix processor in a matrix of mesh-interconnected matrix processors includes an instruction processing pipeline, and a hardware data switch capable of streaming data to/from one or more inter-processor matrix links and/or a matrix processor local memory links in response to execution of a data streaming instruction by the instruction processing pipeline. The data switch can transfer each data stream, which includes multiple words, at wire speed, one word per cycle. After initiating a data stream, the processing pipeline can execute other instructions, including streaming instructions, while a stream transfer is in progress. Different data streaming instructions may be used to transfer data streams from local memory to one or more inter-processor links, from an inter-processor link to local memory, from an inter-processor link to one or more inter-processor links, and from an inter-processor link to one or more inter-processor links and synchronously to local memory.

Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory

Growing community of inventors

Santa Clara, CA, United States of America

Ilie Garbacea