Apple Inc.

Ilia Benkovitch

Nir Tishbi

Ruby Mizrahi

Yonathan Tate

Roy Roth

Michael Jeffet

A receiver includes an interface, a delay line and circuitry. The interface receives data symbols and a clock signal for strobing the data symbols at selected positions. The delay line produces from the clock signal a middle sampling signal, and early and late sampling signals that respectively precedes and succeeds the middle sampling signal. The circuitry samples the data symbols using the middle, early and late sampling signals to produce early and late error signals. Based on the early and late error signals the delay line delays the middle, early and late sampling signals by separate delay values, so as to track both (i) a phase parameter indicative of a deviation between the middle sampling signal and the selected positions of the data symbols, and (ii) a width parameter indicative of a time duration of the data symbols, and to output the data symbols strobed using the middle sampling signal.

Synchronization between data and clock signals in high-speed interfaces

A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells. The processor produces one or more readouts by reading a group of the memory cells using one or more Read Voltages (RVs). Based on the readouts, the processor calculates for a given RV among the RVs a sample of an error signal indicative of a deviation between the given RV and an optimal RV that results in a minimal number of errors in reading the memory cells in the group. The processor applies a filter to the sample of the error signal so as to produce an updated value of the given RV, the filter includes one or more filter taps storing data related to previous samples of the error signal, and reads a second group of the memory cells using the updated value of the given RV.

Tracking of read voltages while reading memory cells

A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

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Rishon Lezion, Israel

Ilia Benkovitch