Silego Technology Inc.

National Semiconductor Corporation

Visic, Inc.

Ilbok Lee

Marcelo Martinez

John Othniel McDonald

Crist Y Lu

Ian Chen

Thomas D Brumett, Jr

Joel A Karp

John A Reed

An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.

Integrated circuit frequency generator

Communicating a power control feedback signal from a system is disclosed. In some embodiments, upon determining how to control input power which may be based at least in part, for example, on an in situ measurement of an operating condition in an operating environment, an appropriate symbol is constructed based upon the determination and is transmitted on a single line. In some embodiments, the single line corresponds to the reference voltage of an associated power supply.

Power management

An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is periodically pulse powered-on to calibrate the electronic oscillator.

Communicating a power control feedback signal

Controlling input power is disclosed. In some embodiments, an in situ measurement of an operating condition in an operating environment is compared to a benchmark, and the comparison is used at least in part to determine whether to change input power.

Controlling input power

Adjusting input power in response to a clock frequency change is disclosed. In some embodiments, a clock signal is input into a buffer, and if an increase in clock frequency is detected at the buffer input relative to the buffer output, the supplied power is increased so that an increased supplied power is provided to an associated system before the increased frequency clock signal is output from the buffer and applied to the system. In some embodiments, the current operating frequency is compared with the operating frequency associated with the next operating state. If the next operating frequency is higher than the current operating frequency, the supplied power is increased, and application of the next operating frequency is delayed so that the next operating frequency is not applied before the increased supplied power is available.

Adjusting input power in response to a clock frequency change

There is provided an improved MOS dynamic random access memory (DRAM) device having an array of dynamic RAM cells accessed by word and bit lines. Each memory cell comprises a single field-effect transistor coupled by its source to the gate of an MOS storage capacitor. The word lines are coupled to their respective memory cells at the gate of the field-effect transistor therein, while the bit lines are coupled to their respective memory cells at the drain of the field-effect transistor. The bit lines are organized into pairs of adjacent polysilicon lines that are coupled to all the memory cells on both sides of the bit lines in an alternating configuration. The word lines are coupled to alternating pairs of cells on opposite sides of the word lines.

Dynamic RAM memory

A semiconductor memory is comprised of a semiconductor substrate having first and second spaced apart arrays of memory cells disposed thereon. A plurality of first pairs of bit lines couple to the cells of the first array, and a corresponding plurality of second pairs of bit lines couple to the cells of the second array. Disposed between each first pair and corresponding second pair of bit lines is one X sense amplifier. This amplifier includes a set node selectively coupled to one bit line of the first pair and to one bit line of the second pair, and a reset node selectively coupled to the opposite bit lines of the first and second pair for selectively sensing charge on the four bit lines.

Growing community of inventors

Los Altos Hills, CA, United States of America

Ilbok Lee