Marvell Israel (misl) Ltd.

Marvell Asia Pte., Ltd.

Marvell International Limited

Marvellworld Trade Ltd.

Ilan Yerushalmi

David Melman

Tal Mizrahi

Ilan Mayer-Wolf

Donald Robert Pannell

Rami Zemach

Carmi Arad

Youval Nachum

Adar Peery

Lior Valency

Yaron Kittner

Yuval Peled

Doron Schupper

Aviram Amir

A packet processor of a network device includes a forwarding engine that is configured to determine egress network interfaces via which packets received by the network device are to be transmitted. The packet processor also includes a header parser configured to parse header information in the packets received by the network device. The header parser includes a first parsing circuit that is configured to parse a first portion of a header of a packet and to prompt a programmable second parsing circuit to parse a second portion of the header. The first portion of the header has a header structure known to the first parsing circuit. The programmable second parsing circuit includes configurable circuitry and a memory to store control information that controls operation of the configurable circuitry to parse the second portion of the header.

Hybrid fixed/programmable header parser for network devices

A network device includes a plurality of network interfaces configured to couple with a plurality of physical network links. A packet processor is configured to process packets received via the plurality of network interfaces. The packet processor includes a path selection engine that is configured to: for each of at least some packets processed by the packet processor, successively make path selection decisions that correspond to respective routing domains within a hierarchical communication network, the path selection decisions for forwarding the packet through the hierarchical communication network.

Hierarchical path selection in a communication network

A switching system comprises a controlling switch and a plurality of port extenders. One of the port extenders includes: at least one upstream port; multiple downstream ports; and a forwarding engine. A forwarding database is populated with entries indicating associations between i) respective network addresses corresponding to devices coupled to downstream ports, and ii) respective local downstream ports. The forwarding database excludes entries corresponding to network addresses corresponding to devices coupled to the at least one upstream port. The forwarding engine is configured to: for a first packet received via one of the local downstream ports, and having a destination network address in the forwarding database, forward the first packet to a different local downstream port indicated by the forwarding database. For a second packet received via one of the local downstream ports, and having a destination network address not in the forwarding database, forward the second packet to the at least one upstream port.

Port extender with local switching

At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.

Flexible header alteration in network devices

A packet received by a network device via a network. A first portion of the packet is stored in a packet memory, the first portion including at least a payload of the packet. The packet is processed based on information from a header of the packet. After the packet is processed, a second portion of the packet is stored in the packet memory, the second portion including at least a portion of the header of the packet. When the packet is to be transmitted the first portion of the packet and the second portion of the packet are retrieved from the packet memory, and the first portion and the second portion are combined to generate a transmit packet. The transmit packet is forwarded to a port of the network device for transmission of the transmit packet via port of the network device.

Method and apparatus for processing packets in a network device

A packet type corresponding to a packet received by a network device is determined. Based on the packet type, one or more header fields to be extracted from a header of the packet are identified. Identifying the one or more header fields includes extracting, from a memory based on the packet type, respective indicators of locations of the one or more header fields and respective indicators of sizes of the one or more header fields. The one or more identified header fields from the header of the packet, based on the respective indicators of locations of the one or more header fields and respective indicators of sizes of the one or more header fields. The packet is then processed based on the one or more header fields extracted from the header. The processing includes deter mining at least one port to which to forward the packet.

Flexible processor of a port extender device

In a method for egress processing packets in a network device, a first stage engine, implemented in hardware, identifies a particular set of computer-readable instructions for a particular packet. The particular set of computer-readable instructions is identified from among a plurality of sets of computer-readable instructions stored in a memory, respective ones of the plurality of sets of computer-readable instructions being for performing different sets of egress processing operations with respect to different packets. A second stage processor, configured to execute computer-readable instructions stored in the memory, executes the particular set of computer-readable instructions, identified by the first stage engine, to perform the corresponding set of egress processing with respect to the particular packet.

A packet received by a network device via a network. A first portion of the packet is stored in a packet memory, the first portion including at least a payload of the packet. The packet is processed based on information from a header of the packet. After the packet is processed, a second portion of the packet is stored in the packet memory, the second portion including at least a portion of the header of the packet. When the packet is to be transmitted the first portion of the packet and the second portion of the packet are retrieved from the packet memory, and the first portion and the second portion are combined to generate a transmit packet. The transmit packet is forwarded to a port of the network device for transmission of the transmit packet via port of the network device

A switching system comprises a controlling switch and multiple port extenders. The controlling switch includes: a plurality of controlling switch ports; and a first packet processor having a first forwarding engine. The first forwarding engine is configured to forward packets received at any controlling switch port to any other controlling switch port. Each of at least some multiple port extenders includes: at least one local upstream port coupled to the controlling switch directly or via another port extender; a plurality of local downstream ports; and a second packet processor having a second forwarding engine and a forwarding database. The second forwarding engine is configured to forward packets i) received at the downstream ports, and ii) for which the forwarding database does not include forwarding information, only to the at least one upstream port. The second packet processor has reduced functionality as compared to the first packet processor.

There is provided a network device disposed at an interface between an access segment and an interconnecting layer of a data center. The network device includes an address cache and an address resolution processor configured to receive an address request addressed to virtual machines in a transmission domain of the network device. The address request requesting a layer 2 address of a target virtual machine in the data center, and specifying a layer 3 address of the target virtual machine. In response to receiving a reply, the network device updates the address cache to include an entry specifying the layer 2 address of an edge device of an access segment which has the target virtual machine having a respective layer 3 address corresponding to the specified layer 3 address.

Scaling address resolution for massive data centers

There is provided a network device disposed at an interface between an access segment and an interconnecting layer of a data center. The network device includes an address resolution processor configured to receive an address request addressed to virtual machines in a transmission domain of the network device. The address request specifying a source layeraddress, requesting a layeraddress of a target virtual machine in the data center, and specifying a layeraddress of the target virtual machine. The network device is further configured to transmit a local message over the first access segment requesting the respective layeraddress of a virtual machine which has the specified layeraddress. In response to receiving a reply, the network device transmits a message to the specified source layeraddress to provide the layeraddress of the network device and the specified layeraddress.

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Hod Hasharon, Israel

Ilan Yerushalmi