Intel Corporation

Mellanox Technologies, Ltd.

Motorola Corporation

Applied Micro Circuits Corporation

Ford Motor Company Limited

Ilan Pardo

Debendra Das Sharma

David J Harriman

Eliezer Weissmann

Mark B Rosenbluth

Sridhar Muthrasanallur

Oren Ben-Kiki

Robert G Blankenship

Mahesh U Wagh

Jasmin Ajanovic

Scott Dion Rodgers

Ohad Falik

Anil Vasudevan

Prashant Sethi

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Peter J Barry

Yuval Yosef

Dror Markovich

Abraham Mendelson

Robert Valentine

Avi Mendelson

Paul S Diefenbaugh

Mikal Hunsaker

Robert E Gough

Yuval Bachrach

Dror Reif

Akshay G Pethe

Gideon Prat

Rafi Ben-Tal

Ido Y Soffair

Ariel Shahar

Avi (Abraham) Mendelson

Idan Burstein

Miriam Menes

Arch D Robison

Pedro Marcuello

Shahaf Shuler

Uria Basher

Ahmad Atamli

James Henry Cownie

Danny Shterman

Evgeny Pimenov

Enrique De Lucas

Alon Naveh

Noam Bloch

Carl Ramey

Devadatta V Bodas

James B Crossland

Stanislav Shwartsman

Niranjan L Cooray

Shlomo Raikin

Anil Aggarwal

John J Vaglica

George Elias

Alexander Joffe

Michael Behar

Justin J Song

Avi Urman

James B Eifert

Hillel Chapman

Christopher J Jackson

Boris Pismenny

Yamin Friedman

Adi Menachem

Omri Kahalon

Oded Lempel

Gal Yefet

Wallace B Harwood, Iii

Peter Paneah

Gil Moran

Michael Cotsford

Rui Xu

Itai Katz

Noam Korem

Gabi Liron

Sayantan Sur

Nathan Y Elnathan

Adi Sapir

Tzuriel Katoa

Saar Tarnopolsky

David Shamir

Tsofia Eshel

Edward Clark Nelson

Nadav Chachmon

Yair Libman

Adi Maymon

Mark E Cummins

Nizan Atias

Mikal C Hunsaker

Avi (Arraham) Mendelson

Ellezer Weissmann

Omer Cohen

Barak Biber

Ohad Fallk

Meni Orenbach

Tomer Bar-On

Ben-Kiki Oren

The technology disclosed herein enables selective clearing of memory regions upon a context switch. An example method includes the operations of: receiving a memory access request referencing a memory region; determining an identifier of a current execution context associated with the memory region; determining an identifier of a previous execution context specified by metadata associated with the memory region; responsive to determining that the identifier of the current execution context does not match the identifier of the previous execution context, updating the metadata associated with the memory region to store the identifier of the current execution context; clearing at least a part of the memory region; and processing the memory access request with respect to the memory region.

Maintaining data confidentiality in shared computing environments

A method includes receiving a network packet into a hardware pipeline of a network device; parsing and retrieving information of the network packet; determining, by the hardware pipeline, a packet-processing action to be performed by matching the information to a data structure of a set of flow data structures; sending, by the hardware pipeline, an action request to a programmable core, the action request being populated with data to trigger the programmable core to execute a hardware thread to perform a job, which is associated with the packet-processing action and that generates contextual data; retrieving the contextual data updated by the programmable core; and integrating the contextual data into performing the packet-processing action.

Programmable core integrated with hardware pipeline of network interface device

A confidential computing (CC) apparatus includes a CPU and a peripheral device. The CPU is to run a hypervisor that hosts one or more Trusted Virtual Machines (TVMs). The peripheral device is coupled to the CPU and to an external memory. The CPU includes a TVM-Monitor (TVMM), to perform management operations on the one or more TVMs, to track memory space that is allocated by the hypervisor to the peripheral device in the external memory, to monitor memory-access requests issued by the hypervisor to the memory space allocated to the peripheral device in the external memory, and to permit or deny the memory-access requests, according to a criterion.

Confidential computing with device memory isolation

A processor includes a memory and a processing core. The processing core is configured to define, in the memory, a jump table that is indexed by a service identifier and includes start addresses for respective service identifier values, to receive a system call that specifies a service identifier value, and to serve the system call by executing program code starting from a start address corresponding to the specified service identifier value.

Processor supporting vectored system calls

A processor includes a set of registers and a processing core. The processing core is configured to execute instructions, including an instruction that causes the core to reset a plurality of the registers in the set.

Processor with instructions for resetting multiple registers

A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

Peripheral component interconnect attributes shared using address bits

An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

Processor with conditional-fence commands excluding designated memory regions

A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.

Expandable queue

In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

Payload cache

Computing apparatus includes a central processing unit (CPU), including at least one core and a cache in physical proximity to the at least one core, with a system memory and a bus connecting the CPU to the memory. A peripheral device is connected to the bus and is configured to write data items via the bus to a buffer in the system memory and to write respective completion reports to the system memory upon writing the data items to the buffer. The peripheral device is configured to detect that the CPU has read a first completion report from the system memory and then read context metadata associated with the first completion report from a given address in the system memory, and is further configured, upon writing a second completion report subsequent to the first completion report and associated with the same context metadata, to stash the second completion report and the context metadata from the given address to the cache.

Prefetching of completion notifications and context

An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

Apparatus and method for a hybrid latency-throughput processor

Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.

Instructions and logic to provide atomic range modification operations

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.

Implementing hierarchical PCI express switch topology over coherent mesh interconnect

A processor is described having logic circuitry of a general purpose CPU core to save multiple copies of context of a thread of the general purpose CPU core to prepare multiple micro-threads of a multi-threaded accelerator for execution to accelerate operations for the thread through parallel execution of the micro-threads.

Apparatus and method for invocation of a multi threaded accelerator

Growing community of inventors

Ramat-Hasharon, Israel

Ilan Pardo