Samsung Electronics Co., Ltd.

Il-Won Seo

Jong-Shin Shin

Jae-Hyun Park

Kyu-Hyoun Kim

Ji-young Kim

Hyun-Wook Lim

Chi-won Kim

Moo-Sung Chae

Hyun-Goo Kim

Myoung-bo Kwak

Hoe-ju Chung

Ju-Hyung Hong

Duck-hyun Chang

Kyu-hyun Kim

An encoding method includes partitioning an input stream into first sub-blocks and second sub-blocks, encoding the second sub-blocks based on a number and location of reference sub-blocks to generate third sub-blocks when at least one of the first sub-blocks corresponds to a forbidden pattern, and rearranging the first sub-blocks and the third sub-blocks to generate an output stream. The reference sub-blocks indicate the second sub-blocks that correspond to a reference pattern and the third sub-blocks includes a redundant information sub-block and non-redundant information sub-blocks. Thus, the encoding method may properly control a direct current (DC) component.

Encoding and decoding method to control a direct current (DC) component, and data processing apparatus performing the same

A read circuit of a disk drive system that adaptively reduces signal-dependent noise including a sequence detector, a signal-dependent adaptive engine and a signal-dependent post-processor. The sequence detector recovers a data sequence from equalized data. The signal-dependent adaptive engine generates signal-dependent coefficients, a mean value and a standard deviation of a signal-dependent error. The signal-dependent post-processor corrects the signal-dependent error.

Read circuit of a disk drive system and method of signal processing thereof

For updating a gain of a loop filter from a timing error signal, a timing signal estimator generates a current timing signal estimation value from a prior timing error estimation value, a prior gain value, and a prior timing signal estimation value. A timing error estimator generates a current timing error estimation value from a timing error accumulation value and the current timing signal estimation value. A current gain value of the loop filter is determined from the current timing error estimation value.

Apparatus for updating gain of loop filter

A spread spectrum clock generator (SSCG) and method of generating a spread spectrum clock (SSC) signal, in which the SSCG may include a controller outputting a given modulation voltage signal based on a difference between an average frequency of a first feedback signal and a comparison frequency signal input thereto, or based on comparison in total phase variations between a second feedback signal and the comparison frequency signal, and a sub-system for generating a first control voltage as a function of an input reference frequency signal and a second feedback signal input thereto. An adder may add the first control voltage signal and the modulation voltage signal to generate a second control voltage signal, and a voltage control oscillator (VCO) may generate the SSC signal based on the second control voltage signal.

Spread spectrum clock generator and method for generating a spread spectrum clock signal

A timing recovery circuit for a receiver may include a timing error detector that generates a timing error based on differences between coefficients of a feed-forward filter and a feed-back filter. The timing recovery circuit may include a loop filter which generates a control voltage signal based on the timing error, and a voltage controlled oscillator that generates a sampling clock for the receiver based on the generated control voltage signal.

Timing recovery circuit and timing recovery method

A semiconductor capable of reducing skew between plural-bit output data by using a plurality of data output drivers and a method thereof. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state in response to signals received from other data output drivers.

Semiconductor device and method of outputting data therein

A digital phase interpolator including a plurality of delay stages to control delay time of an output signal from first and second input signals having different phase delays. The plurality of delay stages are connected serially, have a same internal structure, determine corresponding axes for interpolation in each stage, and each includes a first inverting section for inverting first and second signal inputs from the previous stage, a phase blender for blending outputs of the first inverting section, a second inverting section for inverting outputs of the first inverting section, and a multiplexer for generating input signals for the next stage in response to a selection signal for determining phase delay time of the output signal of the phase interpolator. Total area and current may be reduced by the present invention because the number of inverters comprising each stage is equal.

Growing community of inventors

Seoul, South Korea

Il-Won Seo