Korea Telecommunication Authority

Korea Telecom

Il Song Han

Dae Hwan Kim

Young Jae Choi

This invention relates to a high speed packet switching controller in a telephone switching system which can suitably be applied to a packet controller having large capacity using a neural network chip and maximize the system performance by the optimized switching operation. The high speed packet switching controller comprises a row address decoder for decoding a weight raw address which is inputted thereto, a column address decoder for decoding a weight column address which is inputted thereto, a matrix array for providing the neural network using address signals provided from the row address decoder and column address decoder and outputing varied voltage in accordance with an external weight value, a neural network for producing a final crossbar switching control signal, an external input/output bus for transmitting an output signal of the neural network, and an internal neural data bus for transmitting the address signal output from the row address decoder and column address decoder to the matrix array.

High speed packet switching controller for telephone switching system

Control-type continuous ramp converting apparatus and method therefore. The present invention provides real-time processing of neurons in the neural network, easy implementation and reduction of manufacture cost of high density neurons in the neural network. The present invention comprises a first voltage controlling part for receiving a first voltage from an outside, and for non-linearly increasing a charged voltage in accordance with a differential continuous function of an exponential function; a second voltage controlling part for receiving a second voltage from an outside, and for non-linearly reducing a charged voltage in accordance with a differential continuous function of an exponential function; a charging part for charging an input current, and for providing the charged voltage of the charging part with the second voltage controlling part and an outside; and a plurality of switches for coupling outside and the first and the second voltage controlling part to the charging part, for selectively providing a third voltage from outside, an increased voltage and a decreased voltage based on the voltage of the charging part.

Control-type continuous ramp converting apparatus and method therefore

A multiplier and a neural network synapse capable of removing nonlinear current using current mirror circuits. The multiplier produces a linear current by using MOS transistors operating in a nonsaturation region. The multiplier includes a first current mirror including a plurality of MOS transistors to form a first current and a second current mirror including a plurality of MOS transistors to form a second current, wherein the second current mirror is coupled in parallel to the first current mirror. As a result, the multiplier outputs an output current by subtracting a second current from said first current.

Multiplier and neural network synapse using current mirror having

A multiplier capable of removing nonlinear current using current mirror circuits. The multiplier uses MOSFET and BJT devices by the BiCOMS processes. The multiplier includes three current mirror circuits. A first current mirror includes a BJT Q.sub.3 and a BJT Q.sub.5 and also the BJT Q.sub.3 is coupled in series to the n-channel MOSFET M1 between the voltage V.sub.1 and a ground voltage level. A second current mirror includes a BJT Q.sub.7 and a BJT Q.sub.8. A third current mirror includes a BJT Q.sub.4 and a BJT Q.sub.6. Consequently, input voltage signals V.sub.1 and V.sub.dc applied to the n-channel MOSFETs M1 determine the current I.sub.1 and input voltage signals V.sub.1 and V.sub.2 applied to the n-channel MOSFET M2 determine the current I.sub.2.

Analogue multiplier using MOSFETs in nonsaturation region and current

A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.

MOSFET analog multiplier

A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.

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Seoul, South Korea

Il Song Han