International Business Machines Corporation

Il Park

Kattamuri Ekanadham

Pratap Chandra Pattnaik

Jong-Deok Choi

Mauricio J Serrano

Chung-Lung K Shum

Jose Eduardo Moreira

David S Levitan

Brian R Konigsburg

Seetharami R Seelam

Jennifer A Navarro

David Mui

A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.

Operating a stack of information in an information handling system

A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.

Maintaining data coherence by using data domains

A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.

Enhancing timeliness of cache prefetching

An event tracking hardware engine having N (&#x2267;2) caches is invoked when an event of interest occurs, using a corresponding key. The event tracking engine stores a cumulative number of occurrences for each one of the different kinds of events, and searches in the N caches for an entry for the key. When an entry for the key is found, the engine increments the number of occurrences if no overflow of the cumulative number of occurrences would occur. However, if the incrementing would cause overflow, then instead of incrementing the cumulative number of occurrences, the engine promotes the entry for the event of interest to a next higher cache.

Event tracking hardware

A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction address to provide a first branch target prediction; a first branch table for capturing local past target information of an indirect branch in an encoded form; a second branch table which is a correlation table for storing potential branch targets based on a local branch history and which provides a second branch target prediction when the first branch target prediction is not successful; an exclusion predictor for inhibiting updates of inefficient entries; and a multiplexer to select the predicted target as output.

Target branch prediction using a plurality of tables

A method for prefetching data from an array, A, the method including: detecting a stride, dB, of a stream of index addresses of an indirect array, B, contents of each index address having information for determining an address of an element of the array A; detecting an access pattern from the indirect array, B, to data in the array, A, wherein the detecting an access pattern includes: using a constant value of an element size, dA; using a domain size k; executing a load instruction to load bi at address, ia, and receiving index data, mbi; multiplying mbi by dA to produce the product mbi*dA; executing another load instruction to load for a column address, j, where 1&#x2266;j&#x2266;k, and receiving address aj; recording the difference, aj&#x2212;mbi*dA; iterating the executing a load instruction, the multiplying, the executing another load instruction, and the recording to produce another difference; incrementing a counter by one if the difference and the another difference are the same; and confirming column address j when the counter reaches a pre-determined threshold; executing a load instruction to load bi+dB and receiving index data nextmbi; and executing a load instruction to load Aj+nextmbi*dA, where Aj=(aj&#x2212;mbi*dA) when the column address j is confirmed to prefetch the data from the array, A.

Prefetching indirect array accesses

Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride pattern, detecting an indirect access pattern to define an access window, prefetching candidates within the defined access window, wherein the prefetching comprises obtaining prefetch addresses from a history table, updating a miss stream window, selecting a candidate of a concomitant pair from the miss stream window, producing an index from the candidate pair, accessing an aging filter, updating the history table and selecting another concomitant pair candidate from the miss stream window.

Methods, systems and computer program products for concomitant pair prefetching

An information processing system includes a branch target buffer (BTB) comprising the last next address for the instruction and for receiving an indirect instruction address and providing a BTB predicted target; and next branch target table (NBTT) for storing potential branch targets based on a history of the branch and for providing an NBTT when the a BTB predicted target is not successful. In another embodiment a system comprising a plurality of branch prediction resources dynamically predicts the best resource appropriate for a branch. The method includes predicting a target branch for an indirect instruction address using a resource chosen among the plurality of branch prediction resources; and selectively inhibiting updates of the branch prediction resources whose prediction accuracy does not meet a threshold.

System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries

An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-target branch and logic for reading the memory and identifying a repeated pattern in a plurality of target addresses for a multi-target branch. The information processing system further includes logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified.

Growing community of inventors

White Plains, NY, United States of America

Il Park