Nippon Telegraph and Telephone Corporation

Il-Min Yi

Hideyuki Nosaka

Hiroyuki Fukuyama

Naoki Miura

An amplifier output from an amplifier to an SR latch is used as a feedback signal through a buffer. An adder having a combination of an addition unit and an xh block is provided within the amplifier and transmits a feedback signal (analog signal) generated from the feedback signal FBD (digital signal) by the xh block to the addition unit and adds it to an output from a latch block. In the amplifier, the operation for adding the output from the latch block and the feedback signal occurs during a latch operation in the latch block.

Decision feedback equalizer

An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2reference times corresponding to 2specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.

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Tokyo, Japan

Il-Min Yi