Samsung Electronics Co., Ltd.

Il-Jae Cho

Hyun-Soon Jang

Jin-man Han

A signal line driver operating at high speed and consuming low power and a semiconductor memory device employing the same are disclosed. The signal line driver includes one or more first pull-up transistors, one or more second pull-up transistors, and one or more pull-down transistors. The first pull-up transistor is connected between an external power supply terminal and an output terminal and responds to a first control signal which swings between an internal power supply voltage and a ground voltage. The external power supply terminal receives an external power supply having a voltage level higher than the voltage level of the internal power supply. The first pull-up transistor provides an output signal to the output terminal having the voltage level of the internal power supply voltage minus a predetermined voltage drop. The second pull-up transistor is connected between the internal power supply voltage terminal and the output terminal. The internal power supply terminal receives the internal power supply. The second pull-up transistor increases the voltage level of the output signal to the voltage level of the internal power supply responsive to a second control signal. The pull-down transistor is connected between the output terminal and the ground voltage. The pull-down transistor provides a ground voltage to the output terminal responsive to a third control signal. The semiconductor memory device includes an input buffer, an output buffer, a data input/output line write driver, an input/output line write driver, a data input/output line read driver, and a memory cell array. At least one of the drivers for the semiconductor memory device includes the signal line driver described above.

High speed and low power signal line driver and semiconductor memory

A column decoder of a semiconductor memory device operates in synchronism to an external system clock to decode externally-supplied column addresses. The column decoder has a column select line enable unit which decodes the externally-supplied column addresses and generates a plurality of predecoded column addresses. The column decoder uses a predecoder to predecode the externally-supplied column addresses and generate the predecoded column addresses. The column select line enable unit also uses the predecoder to sample one of the predecoded column addresses in synchronism to the external system clock using an automatic control clock, thereby enabling a column select line. A precharge pulse generator latches one of the predecoded column addresses in response to a first level of the external system clock, triggers to the latched signal in response to a second level of the external system clock, and thereby generates a precharge pulse which is delayed by a specified amount. A column select line enable circuit enables the column select line in response to an enable clock by combining the sampled predecoded column address with the other predecoded column addresses, and which disables the column select line in response to the precharge pulse. The column decoder of the present invention allows for the control of a generation time of the precharge pulse and for the adjusting of a disable interval of the column select line to enhance operation of the column decoder over a wide range of operating frequencies of the semiconductor memory device.

Clock controlled column decoder

A semiconductor memory device reduces the distance occupied between a data path circuit and pads, and minimizes the length of data lines and main input/output lines, thereby improving an operating speed thereof. The semiconductor memory device includes a memory array divided into four array blocks which are independently arranged; a plurality of pads disposed in an area between the upper array blocks and the respective lower array blocks; a data path control circuit disposed in an area between the left array blocks and the respective right array blocks; a data path circuit disposed in a middle center area among the four array blocks; a plurality of data lines connecting the pads to the data path circuit; and a plurality of main input/output lines connecting the memory array to the data path circuit. In this configuration, a distance between the data lines and the main input/output lines and the data path circuit can be minimized.

Semiconductor memory device

A synchronous counter performing a count operation in response to an input of a clock having a fixed frequency. The synchronous counter including a first transmission gate receiving a counter initialization signal and transferring the counter output signal to a carry output node when the counter initialization signal is received during a time period in which the external address signal is not received, and a second transmission gate receiving the counter initialization signal and transferring an address signal to the carry output node when said counter initialization signal is received during a time period in which the external address signal is received.

Growing community of inventors

Suwon, South Korea

Il-Jae Cho