Mitsubishi Denki Kabushiki Kaisha

Ikuo Yasui

Yukihiko Shimazu

Toru Kengaku

Eiichi Teraoka

A semiconductor integrated circuit of master and slave latches and the like that reduces power consumption by supplying a second clock which is a synchronous with a first clock to a slave latch only when the first clock that determines the latch period is supplied to a master latch, discontinuing the supply of the second clock after the master latch completes its latch action in the case that the supply of the first clock to the master latch is discontinued, and discontinuing the supply of clocks when latch action is not required, to reduce loads connected to them.

Semiconductor integrated circuit with master and slave latches

A microprocessor utilizing Harvard Architecture is disclosed with a data space for data storage, an instruction space for instruction storage, and a common space implemented as a high-speed on-chip RAM that functions as a continuous extension of both the data space and the instruction space, for the simultaneous and flexible storage of data and instructions.

Microprocessor with Harvard Architecture

The operation speed of a full adder is increased by avoiding the necessity of forming the inverse signal for adder operation and deleting the time required for passing through an inverter.

Growing community of inventors

Itami, Japan

Ikuo Yasui