Megachips Corporation

Nintendo Co., Ltd.

Ikuo Yamaguchi

Takahiko Sugahara

Takashi Oshikiri

Tetsuo Furuichi

Ryuji Umezu

A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.

Memory control device, semiconductor memory device, memory system, and memory control method

A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.

Memory controller, memory control apparatus, memory device, memory information protection system, control method for memory control apparatus, and control method for memory device

A memory device includes a storage unit having a decryption key storage section that stores key information for decryption and a data storage section that stores to-be-read data requested from the exterior, and a decryption control unit capable of decrypting an externally input encrypted read instruction and address based on the key information stored in the decryption key storage section, and causing data corresponding to the decrypted read instruction and address to be output from the data storage section. The decryption key storage section is composed of arrays of a flash memory.

Memory device

A semiconductor memory includes a memory control section and a memory core section. A command judgment circuit in the memory control section changes the operating mode of the semiconductor memory in response to a command sent from a controller of an information processing apparatus. In a first mode, a decryption process is performed in a command decryption circuit, and data outputted from the memory core section is not scrambled. In a second mode, the decryption process is not performed in the command decryption circuit, and the command outputted from the memory core section is scrambled.

Growing community of inventors

Osaka, Japan

Ikuo Yamaguchi