Ncr Corporation

Sony Corporation

Sony Electronics Inc

Other

Lauffer, Donald K.

Sanwo, Ikuo J.

Tipon, Donald G.

Ikuo J Sanwo

Gregory Howard Milby

Donald K Lauffer

Donald G Tipon

Quynh-Giao X Le

Juei-Po Lin

Joseph Dennis Russell

Mahyar Nejat

Paul M Rostek

Mukesh B Suthar

James A Donahue

William O Kerber

Warren W Porter

Hiroshi Takano

Richard A Daniel

Paul Georgief

John D Simeral

Albert P Chiu

Roger W Boates

Michael A Hoffman

Hyung S Kim

John Flavin

Moo Y Kim

Jean-Robert Clerge

An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.

Open drain driver having enhanced immunity to I/O ground noise

The present invention is a method and apparatus for providing slew rate control. The apparatus comprises a first circuit and a second circuit having an output terminal that is coupled to a first end of the first circuit. The second circuit receives a first input signal and a second input signal. The apparatus further comprises a third circuit having an output terminal that is coupled to the first end of the first circuit. The third circuit also receives the first input signal and the second input signal. The first circuit generates an output signal having a predetermined slew rate, where the output signal has a first state when the first and second input signals are in a first state.

Apparatus and method of providing a programmable slew rate control

A CMOS differential transmitter and matched receiver apparatus and method for transmitting data. The system uses a CMOS bias network to create low voltage swings and optimize the voltage offsets to compensate for variations caused by the manufacturing process, and thereby increase data transmission rates to approximately 1 gigabit per second.

CMOS gigabit serial link differential transmitter and receiver

A high speed test fixture for testing printed circuit board (PCB)-mounted high speed pin grid array (PGA) chips attaches to the solder side (underside) of the PCB to eliminate the need for lead-lengthening adapter sockets. As a result, the testing can be conducted at the actual chip operating speed with reduced noise, rather than at slower speeds required by 'noisy' prior art approaches.

High speed test fixture

A circuit, system, and method for increasing the speed of a bus by reducing the capacitive loading effect of transistors coupled to the bus are provided. The transistors, which are sub-micrometer channel length CMOS transistors, make up a tranceiver comprised of a transmitter and a reciever. The transistors that make up the transciever are coupled to the bus through a pair of Schottky diodes in series. The diode pair is coupled to isolate the bus from the junction capacitance of the transistors. The bus is a multi-segment transmission line with a characteristic impedance. The opposite ends of the transmission line are terminated with the characteristic impedance of the transmission line. The voltage swing of the bus is limited to approximately 1 volt. The pair of Schottky diodes isolate the signal bus line from the capacitive loading effects of the transistor drivers used to drive the voltages on the transmitting end of the bus, especially when the bus is being pulled to a logic high level. This results in minimal loading of the bus line and allows for a faster transmission rate. Speed is also increased by having only approximately a 1 volt swing of the bus line between logic high and logic low voltage states. All devices for this circuit can be fabricated using a standard metal-oxide-semiconductor fabrication process.

High speed CMOS bus transmitter and receiver

A means of converting low voltage CMOS logic levels operating with a 3.3 volts logic level to low voltage PECL logic levels operating with a 3.3 volts supply voltage and a 0.8 volts logic level. The circuit design is process insensitive, and the characteristics of the converter emulate the emitter follower outputs of ECL devices. The converter solves the signal ringing problems caused by open output conditions, and is less susceptible to electromagnetic interference.

Low voltage CMOS to low voltage PECL converter

A memory packaging scheme for high speed computer systems includes, several memory module sockets mounted to a printed circuit board and interconnected by a common set of address, data and control transmission lines within the printed circuit board. The transmission lines are interrupted at each connector. Cooperating memory modules, such as SIMM memory modules are installed in sequence into one or more of the module sockets in accordance with the requirements of the computer system. Installation of a memory module into a memory socket closes the open circuits for each one of the transmission lines at the memory socket, extending the uninterrupted length of the transmission lines to the next memory socket in the sequence. The memory socket and cooperating memory module design thus provides for sizing of the memory board transmission line lengths to accommodate the number of memory modules installed into memory board sockets, thereby eliminating undesirable transmission line effects from occurring within the printed circuit board transmission lines connecting the memory modules.

High speed memory packaging scheme

An apparatus for containing and cooling an integrated circuit device includes a container defining a chamber. The apparatus further includes a conduit positioned in the chamber and having an inner surface and an outer surface, the integrated circuit device being positionable in the chamber and securable to the outer surface of the conduit. In addition, the apparatus includes an insulating member positioned to provide thermal isolation between the container and the conduit.

Apparatus for containing and cooling an integrated circuit device having

An apparatus for containing and cooling an integrated circuit device includes a container defining a chamber, a first portion of the container includes a first heat sink. The apparatus further includes a second heat sink positioned within the chamber, the integrated circuit device being securable to the second heat sink. Moreover, the apparatus includes a cooling device interposed between the first heat sink and the second heat sink. In addition, the apparatus includes an insulator positioned in the chamber so as to provide thermal isolation between a second portion of the container and the cooling device.

Containing and cooling apparatus for an integrated circuit device having

A high speed computer data transfer system includes a transistor diode clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. Also, body effect upon the clamping circuit is lowered. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Clamping circuit for data transfer bus

A CMOS circuit having an input threshold, the CMOS circuit including a first field-effect transistor having a source connected to a first power supply terminal, a drain connected to an output terminal, a gate connected to an input terminal, and a first channel between the source and the drain having a first width and a first length. A programmable field-effect transistor circuit has a gate terminal connected to the input terminal, a drain terminal connected to the output terminal, a source terminal connected to a second power supply terminal, and a second channel circuit between the drain terminal and the source terminal having an effective width and an effective length. Programmable input terminals are connected to the second channel circuit for changing the ratio of the product of the first width times the effective length to the product of the effective width times the first length such that the input threshold voltage of the CMOS circuit is changed responsive to the change of the ratio. By programming the input terminals and selecting the voltages on the first and second power supply terminals, a universal input buffer for conversion of one logic level voltage to another may be provided.

CMOS circuit with programmable input threshold

In a high speed digital computer data transfer system, data bus voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. The output voltages are converted to the proper logic levels with the aid of a differential (sense) amplifier. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

High speed digital computer data transfer system having reduced bus

In a high speed complementary metal-oxide-semiconductor (CMOS) inter-integrated circuit (IC) chip communication system, transmission line voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between CMOS logic levels, thus lowering bus transition and hence data transfer times. The system is versatile, and does not involve typical emitter-coupled logic (ECL) logic levels. Transceivers interfacing between IC chips and the backpanel transmit data in the reduced logic level range on a pre-charged transmission line, and receive and convert data back to CMOS levels. A limiting transistor in the transmitter portion of the transceiver limits logic low level of the transmission line. The receiver portion of the transceiver converts the voltages received to CMOS levels with the aid of a differential (sense) amplifier.

High speed CMOS backpanel transceiver

A high speed computer data transfer system includes a clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

Growing community of inventors

San Marcos, CA, United States of America

Ikuo J Sanwo