Mita Industrial Co., Ltd.

Ikuhiro Omi

Hideo Azumai

Satoshi Iwatsubo

A circuit according to the present invention has an input image processing circuit 11 and an image output processing circuit 12 which are asynchronously operated and a shared memory 18. In addition, it has a memory access signal switching circuit 110. The input image processing circuit 11 and the image output processing circuit 12 access the memory 18 in synchronization with the same memory access synchronous clock SYSCLK, and the access right of the image output processing circuit 12 precedes the access right of the input image processing circuit 11. If one cycle of the processing operation of the input image processing circuit 11 is set longer than the sum of the maximum time period during which the input image processing circuit 11 accesses the memory 18 and the maximum time period during which the image output processing circuit 12 accesses the memory 18, the access to the memory 18 by the input image processing circuit 11 and the access to the memory by the image output processing circuit 12 are not overlapped with each other.

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Osaka, Japan

Ikuhiro Omi