Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Mtekvision Co., Ltd.

Vk Corporation

Ik-Soo Eo

Kyung-Soo Kim

Hee-Bum Jung

In-Gi Lim

Kyung-Jin Byun

Han-Jin Cho

Hyuk Joo Kim

Hyung-Il Park

Jung-Bum Kim

Tae-Joon Kim

Sang-Kyun Kim

Nak-Woong Eum

Seong-joo Lee

Gyeong-Lyong Park

In-San Jeon

Jae-Seok Kim

Mi-Jeong Park

Chung-Wook Suh

Young-Seok Baek

Kyung-tae Han

Hae-bum Jung

Kyungtae Han

Hye-Ju Seo

A sample rate converter and a method of converting a sample rate are disclosed herein. The sample rate converter includes a data delay unit, a clock rate conversion unit, a Lagrange polynomial filter unit, a resample position calculation unit, and a resample position compensation unit. The data delay unit delays signals in response to an input clock signal. The clock rate conversion unit converts the sample rate of the signals. The Lagrange polynomial filter unit performs a filtering function on the signals whose rate has been converted. The resample position calculation unit outputs the value (Dint, dfrac) of the resample position of the signals based on a set resample ratio value. The resample position compensation unit corrects the error value of the signals by applying the value (Dint, dfrac) to the signals, and outputs a final signal.

Sample rate converter and method of converting sample rate

A waveform interpolation speech coding apparatus and method for reducing complexity thereof are disclosed. The waveform interpolation speech coding apparatus includes: a waveform interpolation encoding unit for receiving a speech signal, calculating parameters for a waveform interpolation from the received speech signal, and quantizing the calculating parameters; and a realignment parameter calculating unit for restoring a characteristic waveform (CW) using the quantized parameter, calculating a realignment parameter that maximizes a cross-correlation among consecutive CWs for the restored CW.

Waveform interpolation speech coding apparatus and method for reducing complexity thereof

A hybrid trace back apparatus and a high-speed Viterbi decoding system having the same are disclosed. The hybrid trace back apparatus includes: a register exchanging unit for receiving survivor values of each states from a path metric calculator, and obtaining a block survival value through a register exchange operation as much as a bit length for a block trace back operation; a first storing unit for the register exchange operation; a second storing unit for storing the block survival value obtained through the register exchange operation until the block survival value is written in a block trace back memory; and a block trace back unit for outputting decoded data by performing a block trace back operation while writing a value of the second storing unit.

Hybrid trace back apparatus and high-speed viterbi decoding system using the same

Provided are a flexible bit rate code vector generation method and a wideband vocoder employing the same. This invention implements a flexible bit rate by getting three code vectors which are composed of 24, 16, and 8 pulses, at a time in a search process, through improvement of an algebraic codebook search process in a wideband AMR-WB vocoder. The method includes the steps of: performing a preprocess, wherein the preprocess divides a sub-frame by tracks and decides a pulse position having a maximum value in each track; among a plurality of pulses to be searched, fixing a same number of pulses as the tracks to the position with the maximum value of each track sequentially, and searching optimal positions having a minimum error with a target signal by combining two pulses in two consecutive tracks for the remaining pulses; and creating a code vector with flexible bit rate.

Method for flexible bit rate code vector generation and wideband vocoder employing the same

Disclosed is an apparatus for performing both FHT (Fast Hadamard Transform) and FFT (Fast Fourier Transform). This apparatus determines the phase coefficients as constantly '1' when performing the FHT, and changes the input order of input data to a reverse order of bits when performing the FFT. In addition, the apparatus, which can process a plurality of input data sets simultaneously, classifies the received signals into multi-path signals and multi-antenna signals, thus processing the multi-path signals separately from the multi-antenna signals, or directly processes multi-antenna signals.

Apparatus and method for selectively performing Fast Hadamard Transform or Fast Fourier Transform

A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complexity compared to conventional scheme by embodying the CCK modulation using FFT structure in the OFDM module, and embodying the suboptimal and the optimized CCK modulations using FFT structure in OFDM module. CDMA, OFDM, CCK modules may be integrated as single module.

Apparatus of selectively performing fast hadamard transform and fast fourier transform, and CCK modulation and demodulation apparatus using the same

A multipath searching device includes a radio front-end for converting a received radio signal into a baseband signal and for outputting the baseband signal. A profile calculating unit is included for calculating and outputting the multipath profile of the baseband signal. A first detector determines whether or not the radio signal traveled along a multipath is having a short-delay path by comparing the peak value of the multipath profile with a profile value of a predetermined position time interval before or after the peak of the multipath profile. A path selector receives the multipath profile and the detection result of the first detector, generates time delay information for each path, and separates many paths along which the radio signal traveled. A receiving unit receives the time delay information of the paths, despreads the baseband signal, and combines despread signals.

Apparatus for searching multipath in spread spectrum communications system and method thereof

In the apparatus and method for separating carrier of multicarrier wireless communication receiver system, each carrier separation is performed after a quantization in a wireless communication receiver system such as a received multicarrier CDMA (Code Division Multiple Access) etc., to thereby reduce the whole number of quantizers and separate multicarrier from a received signal. For that, the apparatus for separating the carrier of the multicarrier wireless communication receiver system includes an internal oscillating unit for generating internal multicarrier; a plurality of frequency transition units for respectively down-converting the multicarrier generated by the internal oscillating unit and moving it to frequency of '0' as a frequency center; and a plurality of filtering units for individually filtering the respective carrier moved by the plurality of frequency transition units to the frequency center as the frequency of '0', through a low frequency pass band and for providing it as an input of a rake receiver.

Apparatus and method for separating carrier of multicarrier wireless communication receiver system

A symbol combining method in a Rake receiver, which relates to a method for combining the demodulated multi-path signals in a demodulation process of a code division multiple access communication system. The symbol combining method, a Rake receiver using the symbol combining method and a method for driving the Rake receiver, remarkably reduce a hardware complexity of a FIFO register used to regulate a timing synchronization of each finger in Rake receiver by using a new algorithm in a combining process when a CDMA communication system combines a plurality of multi-path signals therebetween. Whereas a conventional combining algorithm uses an individual FIFO register every finger so as to adjust a timing synchronization of each symbol before combining a demodulated symbol, the inventive combining algorithm performs a symbol combining operation as well as a timing synchronization of a symbol at the same time, and performs a combining action by using only one FIFO register irrespective of the number of fingers.

Symbol combining method for reducing the number of FIFO registers of finger, rake receiver and method for driving the rake receiver

A finite impulse response filter of 1:4 interpolation with 108 taps for outputting filter output data of 8 bits with respect to filter input data of 4 bits includes four shifting and storing unit of 27 bits for unifying bits of filter input data of 4 bits, which is 2's complement to shift and store the bi-unified input data, first selection unit for selecting any one of the input data stored in the four shifting and storing unit of 27 bits, address generating unit for generating addresses of lookup tables corresponding to each of a plurality of filter coefficients groups, first to fourth lookup table groups for generating filter outputs of each filter coefficients group, four accumulating unit for shifting the filter outputs of the filter coefficients groups respectively outputted in parallel from the first to the fourth lookup table groups, and second selection unit for serially converting the outputs from each of the four accumulators in accordance with filter coefficients groups.

Multiplierless finite impulse response filter

An interleaving/deinterleaving processing method, a channel encoding system using it and a computer readable recording media for realizing it is provided. The interleaver includes: an interleaving storing unit for storing data sequence; the writing address generating unit for obtaining inter-location offset of a memory on which symbols are to be written in order to perform a writing operation and for generating a writing address to be practically written on, data and a memory control signal; an address offset generating unit for receiving a middle value (MID_OFF) and a start signal from the writing address generating unit, the middle value and the start signal being used for obtaining an offset between an inter-location offset of the memory; a reading address generating unit for generating increasing the address offset generating unit originated signal to as much as a symbol's memory inter-location offset; the first and the second selecting unit for selecting appropriate signal between a control signal and address in the writing address generating unit and the reading address generating unit transferred writing operation needed reading operation, and in a real interleaving operation needed reading operation; and a third selecting unit for selecting appropriate symbol in the memory output signals and performed from the reading address generating unit transferred interleaving.

Apparatus and method for processing interleaving/deinterleaving with address generator and channel encoding system using the same

A mobile communication method is disclosed, and particularly a power of two length pseudorandom noise sequence generator is disclosed, in which a pseudorandom noise code sequence is generated to use it for a direct sequence spreading of communication signals in a spread spectrum communication system. In the PN sequence generator, a mask value and a comparison value are calculated for shifting the PN sequence output having a length of 2.sup.N as much as wanted, so that the PN sequence can be shifted as much as a predetermined value in response to the single clock signal. In order to generate a PN sequence of the desired timing, a new PN mask value is directly obtained from the current PN mask value and the offset shift value to be shifted, and at the same time, a comparison value corresponding to the mask value is obtained, whereby ultimately a PN sequence having a length of 2.sup.N after shifting the cycle as much as the desired shifting value is obtained. The present invention adopts a method of forming a new comparison value corresponding to the PN mask value by using a comparison value translator, and as a result, the conventional additional circuits for inserting an additional bit into the PN sequence output are not required, and therefore, the constitution of the present invention is very much simplified compared with the conventional apparatus.

Growing community of inventors

Daejon, South Korea

Ik-Soo Eo