Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Ik-Soo Choi

Chang-Youn Hwang

Hae-Jung Lee

Hyung-Hwan Kim

Il-Young Kwon

Bong-Ho Choi

Byoung-Ju Kang

Hong-Gu Lee

Byung-Jun Park

Mi-Hyune You

A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Method for fabricating storage node contact in semiconductor device

A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Method for forming storage node contact plug in semiconductor device

A method for forming a landing contact plug in a semiconductor device is provided. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer over the gate structures; planarizing the inter-layer insulation layer until the gate hard mask is exposed; forming an etch barrier layer on the inter-layer insulation layer; etching a predetermined portion of the inter-layer insulation layer by using the etch barrier layer as an etch barrier to form a plurality of contact holes; forming a conductive layer until the conductive layer fills the contact holes; removing surface roughness created during the formation of the conductive layer by a first etch-back process; and planarizing the conductive layer by a second etch-back process until the gate hard mask is exposed.

Method for forming landing plug contact in semiconductor device

Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC etching process and a defect generation during performing a plug isolation process. The present invention prevents a Pinocchio defect that is a fundamental problem caused by the chemical mechanical polishing (CMP) process and simplifies a subsequent cleaning process performed according to the particles. Accordingly, it is possible to develop products with a high quality and a high speed and to replace the CMP process having a high unit process cost with an etch back process, thereby providing an effect of increasing a price competitiveness.

Method for forming contact plug of semiconductor device

The present invention provides a method of fabricating a capacitor for a semiconductor device. The method includes: forming sequentially a lower electrode and a dielectric layer having a high dielectric constant over a semiconductor substrate which have gone through predetermined processes; forming sequentially a first metal layer and a poly-silicon layer over the dielectric layer; forming an upper electrode pattern by pattering the poly-silicon layer and the first metal layer; forming a second metal layer covering the upper electrode pattern on an entire surface of the semiconductor substrate; and forming an upper electrode constituted with the second metal layer, the poly-silicon layer and the first metal layer by patterning the second metal layer so that the second metal layer is connected with the first metal layer.

Method for fabricating capacitor of semiconductor device

A method for fabricating a resistive load static random access memory (SRAM) capable of providing a high resistive load without local resistance variation, includes a step of forming an isolated layer on a semiconductor substrate having driver and access transistors provided thereto, a step of selectively etching said isolated layer to provide a butting contact region, a step of forming a doped polysilicon layer on a resulting structure, a step of selectively counter-doping said doped polysilicon layer, and a step of patterning said doped polysilicon layer to provide a power supply line, a butting contact and a high load resistor.

Growing community of inventors

Kyoungki-do, South Korea

Ik-Soo Choi