Microsemi Storage Solutions (u.s.), Inc.

Microchip Technology Inc.

Pmc-sierra Us, Inc.

Pmc-sierra, Inc.

Ihab Jaser

Peter Onufryk

Rino Micheloni

Christopher I W Norrie

Alessia Marelli

Luca Crippa

Donia Sebastian

Jack Wynne

Jayesh Patel

Kwok Kong

Xin Guo

William Brent Wilson

Nima Nikuie

Ganesh T Seshan

Mohammad Nikuie

Dan McLeran

An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request's target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.

System and method for centralized management of workload and parallel service of prioritized requests

An apparatus and method for dispatching flash commands. The apparatus includes a plurality of queues, wherein each queue comprises an input to receive a flash command, an output to send a flash command, and an empty signal output to signal when the queue is empty, wherein each queue is assigned a unique, ordered priority. The apparatus includes a selector comprising a plurality of flash command inputs, a flash command output to a flash target, and a selection input, wherein each flash command input is coupled to a corresponding queue output. The apparatus includes an arbiter comprising inputs receiving each queue empty signal and receiving a lock bit from the flash command output of the selector and comprising a selection output coupled to the selection input of the selector. The flash command comprises a lock bit and a plurality of control bits to output to control inputs on a flash target.

System and method for enhancing flash channel utilization

A system (e.g., NVMe controller) for managing access to a memory resource by multiple users may include memory storing function queue categorizations for function queues associated with each user, and circuitry to store and execute a multi-user arbitration algorithm that arbitrates access to the memory resource by the multiple users. The function queue categorizations assign a function category to each function queue associated with each user. The multi-user arbitration algorithm includes (a) selecting an intra-user winning function queue for each respective user by performing an intra-user function queue arbitration of the function queues associated with the respective user based on the function queue categorizations associated with the arbitrated function queues, (b) selecting an inter-user winning function queue by performing an inter-user function queue arbitration of the intra-user winning function queues selected for the multiple users, and (c) serving a function from the inter-user winning function queue to the memory resource.

System for managing access to a memory resource by multiple users

A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.

System and method for higher quality log likelihood ratios in LDPC decoding

A line of data is read from a line of memory. Intended data is specified by a random location and a random size within the line of memory. The line of data is moved into temporary storage. The line of data and a zero are multiplexed using a control signal to output a line of adjusted data which is automatically aligned to an initial point in an XOR buffer. A starting index of the intended data within the line of adjusted data corresponds to the initial point within an XOR buffer. An XOR operation is performed on the line of adjusted data and a line of data read from the XOR buffer to obtain a modified line of XOR data. The modified line of XOR data is written back to the XOR buffer at the same buffer locations as the line of data read from the XOR buffer.

Apparatus and method for minimizing exclusive-OR (XOR) computation time

A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.

System and method for accumulating soft information in LDPC decoding

An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.

Memory controller and integrated circuit device for correcting errors in data read from memory cells

Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.

Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values

Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.

Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system

A nonvolatile memory controller includes a host controller interface, processors, a message networks and a data network. The host controller interface includes a command fetch module, command assembly buffers, and a command dispatch module. The command fetch module retrieves nonvolatile memory commands from a host processing unit. The command assembly buffers store the nonvolatile memory commands retrieved from the host processing unit. The command dispatch module generates request message packets including the nonvolatile memory commands. The message network routes the request message packets to the processors. The processors process the nonvolatile memory commands in the request message packets for controlling operation of the nonvolatile memory controller.

Nonvolatile memory controller with host controller interface for retrieving and dispatching nonvolatile memory commands in a distributed manner

A nonvolatile memory controller processes a nonvolatile memory command and generates a completion status for the nonvolatile memory command. The nonvolatile memory controller transmits the completion status to a host processing unit for storage in a completion queue of the host processing unit. An interrupt manager in the nonvolatile memory controller determines the completion queue contains an unprocessed completion status and generates an interrupt message packet. The nonvolatile memory controller transmits the interrupt message packet to the host processing unit for triggering an interrupt in the host processing unit and alerting the host processing unit to the unprocessed completion status.

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San Jose, CA, United States of America

Ihab Jaser