Intel Corporation

Igor Yanover

Stanislav Shwartsman

Zeev Sperber

Raanan Sade

Robert Valentine

Elmoustapha Ould-Ahmed-Vall

Mark Jay Charney

Bret L Toll

Jesus Corbal

Ron Gabor

Menachem Adelman

Dan Baum

Rinat Rappoport

Yuri Gebil

Joseph Nuzman

Shlomo Raikin

Gavri Berger

Alexander F Heinecke

Milind Baburao Girkar

Barukh Ziv

Liron Zur

Gal Ofir

Guy Patkin

Simon Rubanovich

Alexander Gendler

Lihu Rappoport

Ahmad Yasin

Tomer Stark

George Leifman

Sagi Meller

Lev Makovsky

Amit Gradstein

Jared Warner Stark, Iv

Yiftach Gilad

Assaf Zaltsman

Elkana Korem

Haim Granot

Enrico Perla

Hanan Shomroni

Daniela Kaufman

Edo Hachamo

Efraim Rotem

Carlos V Rozas

Nir Rosenzweig

Xiang Chris Zou

Robert S Chappell

Alaa R Alameldeen

Abhishek Basak

Ofer Levy

Sebastian Winkel

Ethan Schuchman

David W Burns

Oleg Margulis

Polychronis Xekalakis

Vineeth Mekkat

Gabi Malka

Jose Yallouz

Francis McKeen

Alex Gerber

Ron Schneider

Pavel I Kryukov

Andrey Kluchnikov

Jared W Stark

Fangfei Liu

Ron Shalev

Michael D Tucknott

Omer Vikinski

Eyal Hadas

Kamil Garifullin

Ron Rais

Muhammad Taher

Prakash Math

Michael S Bair

Tomer Weiner

Saeed Kharouf

Sumit Ahuja

Pankaj Raghuvanshi

Yongjun Park

Levy Ofer

Leslie A Ong

David Zysman

Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

Apparatuses, methods, and systems toprecisely monitor memory store accesses

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

Systems, methods, and apparatuses for matrix operations

An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

Apparatus and method for power virus protection in a processor

Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

Apparatuses, methods, and systems to precisely monitor memory store accesses

An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

Memory tagging apparatus and method

Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

Restricted speculative execution mode to prevent observable side effects

An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

Memory tagging metadata manipulation

Systems, methods, and apparatuses relating to hardware for split data translation lookaside buffers. In one embodiment, a processor includes a decode circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, and a memory circuit comprising a load data translation lookaside buffer circuit and a store data translation lookaside buffer circuit separate and distinct from the load data translation lookaside buffer circuit, wherein the memory circuit sends a memory access request of the instructions to the load data translation lookaside buffer circuit when the memory access request is a load data request and to the store data translation lookaside buffer circuit when the memory access request is a store data request to determine a physical address for a virtual address of the memory access request.

Hardware for split data translation lookaside buffers

Systems, methods, and apparatuses for tile load

Growing community of inventors

Yokneam Illit, Israel

Igor Yanover