Microchip Technology Inc.

Igor Wojewoda

Stephen Bowling

Rodney J Drake

Yong Yuenyongsgool

Joseph W Triece

Randy L Yach

Bryan Kris

Michael Simmons

Roshan Samuel

Brian E Boles

Stephen D Allen

Jennifer Yuan Chiao

James E Bartling

Alex Dumais

Thomas S Spohrer

Gaurang Kavaiya

Tim Phoenix

Mike Catherwood

Manivannan Balu

Dave Mickey

Brian Fall

Jason Tollefson

Steve Bradley

Steve Allen

Calum Wilke

Michael I Catherwood

Kevin L Kilzer

Sumit K Mitra

Rodney J Pesavento

David Mickey

Cristian P Masgras

Brant Ivey

Edward Brian Boles

Darrel Johansen

Timothy J Phoenix

Naveen Raj

Calum Wilkie

Cobus Van Eeden

Sergey Pavlov

Michael S Pyska

Vincent Sheard

Joseph Kanellopoulos

Samar Naik

Jonathan Brant Ivey

Pavan Kumar Bandarupalli

Mei-Ling Chen

Jim Pepping

Anton Alkhimenok

Dereck Fernandes

Kim Otten

Sudhir Bommena

Vijay Dubey

Michael Pyska

A temperature-compensating clock frequency monitor circuit may be provided to detect a clock pulse frequency in an electronic device that may cause erratic or dangerous operation of the device, as a function of an operating temperature of the device. The temperature-compensating clock frequency monitor circuit include a temperature sensor configured to measure a temperature associated with an electronic device, a clock having an operating frequency, and a frequency monitoring system. The frequency monitoring system may be configured to determine the operating frequency of the clock, and based at least on (a) the operating frequency of the clock and (b) the measured temperature associated with the electronic device, generate a corrective action signal to initiate a corrective action associated with the electronic device or a related device. The temperature sensor, clock, and frequency monitoring system may, for example, be provided on a microcontroller.

Temperature compensated clock frequency monitor

A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.

Integrity monitor peripheral for microcontroller and processor input/output pins

A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

Fault tolerant clock monitor system

A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

Bit manipulation capable direct memory access

In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

Multi-processor core device with MBIST

A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

Low-pin microcontroller device with multiple independent microcontrollers

A microcontroller device has a housing with a plurality of external pins a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

Dual boot panel SWAP mechanism

A multi-boot device capable of booting from a plurality of boot devices, each storing a boot image. The multi-boot device determines which boot device to load based on sequence numbers assigned to each of the boot devices. Some embodiments will make this determination using only hardware operations. The multi-boot device compares the sequence numbers of the available boot devices in order to determine the boot image to be loaded. The address of the selected boot image is then mapped to the device's default boot vector. The remaining images are likewise mapped to a secondary boot memory. The device then boots from the default boot vector. The user can change the boot device to be loaded by modifying one or more of the boot sequence numbers. The boot images can be updated without resetting the device by switching execution to and from boot images in the secondary boot memory.

Boot sequencing for multi boot devices

A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Analog-to-digital conversion with micro-coded sequencer

A processor according to embodiments comprises an on-board sample rate converter for converting a source audio signal that is sampled at a first sampling rate to an output audio signal that is sampled at a second sampling rate. The sample rate converter utilizes a master clock signal in converting the audio signal. The sample rate converter selects the master clock signal from available reference clock signals, such as an on-chip system clock or a bus interface clock, and scales the frequency of the selected clock signal to generate the master clock signal with the frequency of the second sampling rate.

Flexible clocking for audio sample rate converter in a USB system

A method for hot swapping program code includes defining a predetermined range of new code from which to execute; identifying from the new code one or more system components which require a reinitialization or reset; reinitializing or resetting the one or more system components; and executing the new code.

Minimizing switchover time in a hot swappable program memory

A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system dock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock.

Dithering circuit for serial data transmission

A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: &#x2014;a timer being clocked by an independent clock signal; &#x2014;a comparator coupled with a timer register of said timer and having an output generating an output signal; &#x2014;an event register coupled with said comparator; &#x2014;a delta time register; and &#x2014;an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.

Scheduling events in a microprocessor using a plurality of delta time registers arranged as a sequence buffer and indicating a sequence position of the sequence buffer to process an event

A fluorescent lamp light intensity dimming control generates a pulse width modulation (PWM) signal at about a fifty percent duty cycle and has very fine frequency change granularity to allow precise and smooth light dimming capabilities. Intermediate PWM signal frequencies between the frequencies that are normally generated from values in a period register of the PWM generator are provided with a variable frequency clock source to the PWM generator. Selection of each frequency from the plurality of frequencies available from the variable frequency clock source may be determined from a value stored in a variable frequency clock register. A microcontroller may be used to select appropriate frequencies for dimming control of the fluorescent lamp from the variable frequency clock source, and the period and duty cycle values used in generating the PWM signal at about a fifty percent duty cycle.

High resolution pulse width modulation (PWM) frequency control using a tunable oscillator

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Tempe, AZ, United States of America

Igor Wojewoda