Mellanox Technologies, Ltd.

Igor Voks

Ariel Shahar

Roee Moyal

Lior Narkis

Noam Bloch

Dotan David Levi

Idan Burstein

Gil Bloch

Daniel Marcovitch

Richard Leigh Graham

Shay Aisman

Dror Bohrer

Gil Kremer

Dotan Finkelshtein

Eliel Peretz

Liel Peled

Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.

Dynamic memory allocation using a shared free list

A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

Cross address-space bridging

A computing device which may include a hardware-configurable device reconfigurable to perform a series of logical operations to determine, based on parameters related to execution of a job received by the hardware-configurable device, whether or not the job is permissible for execution.

Post-tapeout reconfigurable device

A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

Memory-based synchronization of distributed operations

A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

Size reduction of completion notifications

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Zichron Yaakov, Israel

Igor Voks