Advanced Micro Devices Corporation

Applied Materials, Inc.

Globalfoundries Inc.

International Business Machines Corporation

Igor V Peidous

Linda R Black

Rohit Pal

Frank Wirbeleit

Andy C Wei

Thorsten E Kammler

David E Brown

Martin Gerhardt

Patrick Press

Michael G Ward

Paul Raymond Besser

Judson Robert Holt

Huicai Zhong

Byeong Yeol Kim

Michael D Armacost

Rolf Stephan

Swaminathan T Srinivasan

Peter I Porshnev

Mario M Pelella

Christopher D Sheraw

Xiaomeng Chen

Victor Ku

Jeremiah T Pender

Yen B Ta

Ryan James Patz

Andrew Darlak

Joe Piccirillo

Sunny Chiang

David Brown

An integrated circuit that includes: providing a substrate including a support structure, a dielectric layer, and a variable thickness film processed to include the dielectric layer within a recess of the variable thickness film; forming a gate over the variable thickness film; and forming a channel and a source/drain within the variable thickness film.

Integrated circuit employing variable thickness film

Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.

Methods of forming a metal silicide region in an integrated circuit

Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer.

Methods to adjust threshold voltage in semiconductor devices

Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.

Method for fabricating interconnect structures for semiconductor devices

By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the &#x3c;100&#x3e; direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.

Methods for fabricating a stressed MOS device

Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer

Stress enhanced transistor

Methods for fabricating low contact resistance CMOS integrated circuits are provided. In accordance with an embodiment, a method for fabricating a CMOS integrated circuit including an NMOS transistor and a PMOS transistor disposed in and on a silicon-comprising substrate includes depositing a first silicide-forming metal on the NMOS and PMOS transistors. The first silicide-forming metal forms a silicide at a first temperature. At least a portion of the first silicide-forming metal is removed from the NMOS or PMOS transistor and a second silicide-forming metal is deposited. The second silicide-forming metal forms a silicide at a second temperature that is different from the first temperature. The first silicide-forming metal and the second silicide-forming metal are heated at a temperature that is no less than the higher of the first temperature and the second temperature.

Methods for fabricating low contact resistance CMOS circuits

A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.

Stress enhanced transistor and methods for its fabrication

A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.

Stressed MOS device

A method for fabricating dual material gate structures in a device is provided. The dual material gate structures have different gate electrode materials in different regions of the device. In one embodiment, the method includes providing a substrate having a patterned first gate electrode and a patterned first gate dielectric layer disposed on the substrate, removing a portion of the first gate electrode from the substrate to define a trench on the substrate, and filling the trench to form a second gate electrode.

Methods for fabricating dual material gate in a semiconductor device

Field effect transistors and methods for fabricating field effect transistors are provided. A method, in accordance with an exemplary embodiment of the invention, comprises forming a polycrystalline silicon gate electrode overlying a silicon substrate. The gate electrode has two parallel sidewalls. Two sidewall spacers are fabricated overlying the silicon substrate. Each of the two sidewall spacers has a sidewall that is adjacent to one of the two parallel sidewalls of the gate electrode. A portion of the gate electrode between the two sidewall spacers is removed.

Field effect transistors and methods for fabricating the same

A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Stress enhanced MOS transistor and methods for its fabrication

Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

Growing community of inventors

Loudonville, NY, United States of America

Igor V Peidous