Guzik Technical Enterprises

Igor Tarnikov

Anatoli B Stein

Alexander M Taratorin

Semen P Volfbeyn

Lauri Viitas

Nahum E Guzik

Valeriy Serebryanskiy

Vladislav Anatolievich Klimov

Valeriy Serebryanski

A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.

Digital down converter with equalization

Digital signal acquisition system is triggered when an input waveform matches a known reference waveform. This is achieved by calculating a stream of error metric values defined as a sum of absolute values of differences between incoming and reference samples. An error metric is calculated using only byte operations, which is advantageous for hardware implementation. A waveform trigger is determined by a sample index corresponding to a minimum value of the error metric and corresponds to a best match between input and reference waveforms. A waveform trigger is used for synchronous averaging and estimating time domain noise voltage. A reference waveform updates in poor SNR conditions to provide robust estimates of time domain noise by reducing reference waveform jitter.

Method and apparatus for data acquisition with waveform trigger

A two-stage digital down-conversion device for optimal detection of varying RF pulses incorporates a front end analog to digital converter (ADC), which samples an input RF signal and performs a first stage digital down conversion in wide bandwidth by means of two digital local oscillator multipliers, low pass filters and decimators. A stream of first stage quadrature I and Q samples is analyzed by a first stage I/Q processor. The I/Q processor generates an RF pulse trigger based on a first-stage envelope signal, center frequency and frequency span data which are used for a second stage narrow band digital down-conversion. The second stage digital down-conversion is based on mixing the first stage I and Q data samples with a second stage local oscillator, further low pass filtering and decimation using a second bandwidth. A stream of second stage I/Q quadrature samples has an optimal signal to noise ratio and allows accurate estimation of RF pulse parameters (magnitude, phase and frequency) by means of a second I/Q signal processor and/or by storing second I/Q data for subsequent processing and analysis.

Two-stage digital down-conversion of RF pulses

An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory. The trigger equalizer and a memory equalizer are configured for consecutive operation so that, in an acquisition mode, the memory equalizer receives as its input, a digitized signal from the ADC that has been pre-processed in the trigger equalizer, and the memory equalizer corrects only the residue of misalignments and frequency distortions that remain after the trigger equalizer operation.

Acquisition device with multistage digital equalization

A data acquisition device incorporates a front end analog-to-digital converter (ADC), which is responsive to an applied analog input signal, sample that signal and provide digital data representative of the sampled signal. The digital data is applied to a data channel connected to a data acquisition memory, which stores data values representative of the sampled analog input signal. The digital data from the ADC is also applied to a real time a trigger channel connected to a composite function trigger equalizer and filter, a trigger processor and to a trigger memory. The trigger channel operates in real time to identify trigger events and store real-time trigger event occurrence signals in the trigger memory. A controller reads out the stored data values from the data acquisition memory by way of a data equalizer, in synchronism with corresponding real-time trigger event occurrence signals from the trigger memory.

Data acquisition device with real time digital trigger

Analysis of a read back signal in a magnetic recording device is disclosed. The read back signal is converted to a digital read back signal, and a low frequency component of the digital read back signal is restored. A sample clock is recovered from the restored digital read back signal, and the restored digital read back signal is averaged using the recovered sample clock. A timing error is calculated based at least in part on the averaged restored digital read back signal.

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Palo Alto, CA, United States of America

Igor Tarnikov