Cypress Semiconductor Corporation

Wacom Co., Ltd.

Longitude Flash Memory Solutions Ltd.

Synaptics Corporation

Atmel Corporation

University of California

Parade Technologies, Ltd.

Monterey Research, LLC

Igor Polishchuk

Sagy Charel Levy

Krishnaswamy Ramkumar

Kishore Sundara-Rajan

Esat Yilmaz

Vemund Kval Bakken

Trond Jarle Pedersen

John R Logan

Joo Yong Um

James D Lyle

Yassar Ali

Edward L Grivna

Helmut Puchner

Chenming Hu

Tsu-Jae King

Ying Wang

Jeong Soo Byun

Maroun Khoury

Ravindra Manohar Kapre

Sharmin Sadoughi

Min Chin Chai

Browley Xiao

Nelson Chow

Fred Keiser

Pushkar Ranade

Adam L Schwartz

Tom R Vandermeijden

Vasyl Mandziy

Victor P Drake

Oliver Pohland

Qingbiao Deng

Shotaro Saito

Michael Cornstock

Krishnaswarny Ramkumar

Victor Drake

An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Nonvolatile charge trap memory device having a high dielectric constant blocking region

In one embodiment, a stylus comprising an accelerometer operable to detect an acceleration in response to a touch to the body and initiate a pre-determined function, a method of using same, and one or more non-transitory computer-readable storage media embodying logic.

Executing gestures with active stylus

In one embodiment, a stylus receives a first signal from a first electrode of the stylus, the stylus being operable to communicate wirelessly with a device through a touch sensor of the device; receives a second signal from a second electrode of the stylus, the second signal being a reference signal and the second electrode being a reference electrode; and compares the first signal with the second signal.

Differential sensing in an active stylus

An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Memory transistor with multiple charge storing layers and a high work function gate electrode

In one embodiment, a stylus with one or more electrodes and one or more computer-readable non-transitory storage media embodying logic for transmitting signals wirelessly to a device through a touch sensor of the device has one or more sensors for detecting movement of the stylus.

Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor. Other embodiments are also disclosed.

Flash memory device and method

Growing community of inventors

Fremont, CA, United States of America

Igor Polishchuk