Synopsys, Inc.

University of Michigan

William Marsh Rice University

Igor L Markov

Kenneth S McElvain

Farinaz Koushanfar

Jarrod Alexander Roy

Valeria Bertacco

Kai-Hui Chang

Ilya Wagner

Hector J Garcia-Ramirez

The disclosed method and computer-readable medium allow efficient simulation of both stabilizer and non-stabilizer states in general quantum circuits on a classical computer by maintaining global phases and orthogonalizing linear combinations of stabilizer states during simulation. This is accomplished by representing arbitrary quantum states as superpositions of stabilizer states, which may be implemented using one or more stabilizer frames. Each stabilizer frame includes a stabilizer matrix, one or more phase vectors corresponding to the stabilizer states, and an amplitude vector corresponding to the global phases of each stabilizer state. Orthogonality is maintained throughout the simulation for efficient computation and measurement. Some embodiments utilize a multiframe representation of the quantum state to reduce the number of stabilizer states required to represent the quantum state, which multiframe representation may also be used to implement parallel simulation.

Methods for general stabilizer-based quantum computing simulation

Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.

Approximate functional matching in electronic systems

Techniques are able to lock and unlock and integrated circuit (IC) based device by encrypting/decrypting a bus on the device. The bus may be a system bus for the IC, a bus within the IC, or an external input/output bus. A shared secret protocol is used between an IC designer and a fabrication facility building the IC. The IC at the fabrication facility scrambles the bus on the IC using an encryption key generated from unique identification data received from the IC designer. With the IC bus locked by the encryption key, only the IC designer may be able to determine and communicate the appropriate activation key required to unlock (e.g., unscramble) the bus and thus make the integrated circuit usable.

Protecting hardware circuit design by secret sharing

Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock.

Temporally-assisted resource sharing in electronic systems

A computer executable tool facilitates integrated circuit design and debugging by working directly at the Register Transfer Level, where most design activities take place. The tool determines when an integrated circuit design produces incorrect output responses for a given set of input vectors. The tool accesses the expected responses and returns the signal paths in the integrated circuit that are responsible for the errors along with suggested changes for fixing the errors. The tool may operate at the RTL, which is above the gate-level abstraction which means that the design errors will be much more readily understood to the designer, and may improve scalability and efficiency.

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Ann Arbor, MI, United States of America

Igor L Markov