Xilinx, Inc.

Igor Kostarnov

Richard Lewis Walke

Andrew M Whyte

A circuit structure efficiently multiplies a first and second number. The circuit structure includes multipliers for the pairs of three-bit digits of the first number and three-bit digits of the second number. The multipliers produce six-bit partial products from the pair of three-bit digits of the first and second numbers. Each multiplier includes look-up tables receiving the pair of three-bit digits of the first and second numbers. A summing-tree circuit includes adders arranged in a series of levels, the adders in an initial one of the levels producing partial sums from the six-bit partial products from the multipliers, and for each first and successive second ones of the levels in the series, the adders in the second level producing another plurality of partial sums from the partial sums from the first level. A last one of the levels includes the adder that produces a product of the first and second numbers.

Circuit structure for multiplying numbers using look-up tables and adders

Architecture of a digital signal processing engine and method for digital signal processing therewith are described. Instruction memory stores an instruction which has at least one opcode which is selected from a group consisting of a control opcode, a digital signal processing (DSP) opcode, and a memory opcode. A digital signal processing engine includes a controller for receiving the control opcode, a DSP core for receiving the DSP opcode, and a memory interface for receiving the memory opcode. The controller, the digital signal processing core, and the memory interface are separate pipelines at least two of which have different numbers of stages. The controller may include an arithmetic logic unit, a base address regfile, and a branch/decode circuit.

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Tokyo, Japan

Igor Kostarnov