Infineon Technologies Ag

Other

International Business Machines Corporation

Igor Kasko

Walter Hartner

Volker Weinrich

Hermann Wendt

Nicolas Nagel

Rainer Bruchhaus

Gregory Costrini

Thomas Mikolajick

John Patrick Hummel

Kia-Seng Low

Matthias Kroenke

Wolfgang Raberg

Frank S Hintermaier

Gerhard Enders

G&uuml;nther Schindler

Gerhard Beitel

Matthias Kr&ouml;nke

Frank Findeis

Günther Schindler

Annette S&auml;nger

Robert Primig

Michael R&ouml;hner

A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.

Spacer integration scheme in MRAM technology

The invention relates to a method for producing ferroelectric capacitors that are structured using the stack principle and that are used in integrated semiconductor memory chips. The individual capacitor modules have an oxygen barrier between a lower capacitor electrode and an electrically conductive plug. At a site where it is not covered by the corresponding oxygen barrier, an unstructured adhesive layer is oxidized by the oxygen arising during the tempering process of the ferroelectric and forms insulating segments at the site in such a way that the lower capacitor electrodes of the ferroelectric capacitors are electrically insulated from one another. This makes it possible to dispense with structuring the adhesive layer. Furthermore, the layer serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

Method for producing ferroelectric capacitors and integrated semiconductor memory chips

A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.

Method of manufacturing a ferroelectric capacitor configuration

A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.

Method for fabricating a semiconductor memory device

Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a conductive plug. An oxygen diffusion barrier is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. An oxygen rate of the adhesive layer and the diffusion coefficient of oxygen in the material of the adhesive layer dependent on the temperature are determined. A diffusion coefficient of silicon in the material of the adhesive layer, dependent on the temperature, is determined. A temperature range for the RTP step from the two diffusion coefficients, determined for a predetermined layer thickness and layer width of the adhesive layer and the oxygen diffusion barrier is calculated, therefore, the siliconization of the adhesive layer occurs more rapidly than its oxidation.

Method for fabricating ferroelectric memory cells

A capacitor electrode is produced with an underlying barrier structure. A barrier incorporation layer is used and a CMP (chemical mechanical polishing) process is employed in order to produce the barrier structure. The capacitor electrode with an underlying barrier structure is produced by depositing a barrier layer on a semiconductor substrate; forming a barrier structure from the barrier layer with a lithographic mask and an etching step; depositing a barrier incorporation layer covering the barrier structure and surrounding regions; and removing the barrier incorporation layer with chemical mechanical polishing until the barrier structure is uncovered, to thereby form the capacitor electrode above the barrier structure.

Method of producing a capacitor electrode with a barrier structure

A semiconductor device ( ) and method of fabrication thereof, wherein a plurality of first conductive lines ( ) are formed in a dielectric layer ( ) over a substrate ( ), and an insulating cap layer ( ) is disposed over the first conductive lines ( ) and exposed portions of the dielectric layer ( ). The insulating cap layer ( ) is patterned and etched to expose stack portions of the first conductive lines ( ). A conductive cap layer ( ) is deposited over the exposed portions of the first conductive lines ( ). A magnetic material stack ( ) is disposed over the insulating cap layer ( ), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer ( ) and conductive cap layer ( ) protect the underlying first conductive line ( ) material during the etching processes.

Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers

The invention relates to a microelectronic structure. In the structure, an oxygen-containing iridium layer is embedded between a silicon-containing layer and an oxygen barrier layer. The iridium layer is especially produced by a sputter process in an oxygen atmosphere with a low oxygen content. The oxygen-containing iridium layer is stale at temperatures up to 800&deg; C. and withstands the formation of iridium silicide upon contact with the silicon-containing layer. Such micro-electronic structures are preferably used in semiconductor memories.

Capacitor electrodes arrangement with oxygen iridium between silicon and oxygen barrier layer

A method for fabricating a patterned layer from a layer material. The method includes steps of: providing a substrate with at least one target region and at least one migration region; applying a layer material; adding a material to the layer material; and performing a heat treatment such that the layer material migrates from the migration region to the target region and a layer which is self-aligned and self-patterned with respect to the target region is formed. The method has the advantage that the layer material, which can often only be etched with difficulty, does not have to be patterned directly. The desired structure of the layer is predetermined by preliminarily structuring the substrate into a target region and a migration region, and is produced by the migration of the layer material as a result of the heat treatment.

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Fishkill, NY, United States of America

Igor Kasko