Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Igor Genshaft

Marina Frid

Amir Shaharabany

Yacov Duzly

Einat Inna Zevulun

Vered Kelner

Eran Sharon

Yehuda Hahn

Gadi Vishne

Nicholas Thomas

Michal Silbermintz

Jonathan Journo

Avi Klein

Galya Utevsky

The present disclosure generally relates to improved consolidation in dual-layer FTL. In preparation for the next control sync, the controller will generate a copy the uRegions uHeaders and will continue updating the uLayer uRegion with new uRun entries. After completing the control sync operation, the controller will then select the best consolidation candidate based on comparing the uRegion uHeaders with their copy and determining the uRegion with the maximum uRuns difference or the greatest number of uRun updates in case the uRun updates difference is less than a threshold. The controller then reads the selected mSets from the flash memory to its cache and merges the updated uRuns with the cached mSets.

Efficient consolidation for two layer FTL

The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the uLayer capacity and efficacy. The disclosure provides guidance on how to synchronize the uLayer consolidations efficiently and preventing trapping of unused uRegions in the uLayer that reduces the uLayer capacity and efficiency. The synchronizing is between the uLayer consolidation to the mLayer and the mBlock compaction process such that the smaller uLayer efficacy will not be reduced due to trapped uRegions that are less frequently updated.

Finding and releasing trapped memory in uLayer

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to relocate first valid data from a first source block to a destination block, relocate second valid data from a second source block to the destination block, determine that the destination block is closed, re-mark the first and second source block with a second indication, and erase the source blocks that have the second indication. The first source block and the second source block are marked with a first indication after each respective data is relocated. The first indication indicates that the source block cannot be freed. The second indication indicates that the destination block is closed and the associated source blocks can be erased. Prior to closing the destination block, parity data may be generated for the data of the destination block and programmed to the destination block.

Data relocation with protection for open relocation destination blocks

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.

Data mapping comparison for improved synchronization in data storage devices

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a deallocation command corresponding to a plurality of deallocation requests, where each of the plurality of deallocation requests corresponds to a logical block address (LBA) range, determine that at least one of the plurality of deallocation requests is an unaligned deallocation request, generate a tag for metadata for the unaligned deallocation request, wherein the tag for the metadata includes a direction bit and a length bit, concatenate the metadata including the tag to an LBA range of the unaligned deallocation request, and complete the deallocation command using the metadata including the tag. Aligned deallocation requests are stored in a buffer. The concatenated unaligned deallocation requests are completed prior to completing the aligned deallocation requests from the buffer.

Aligned and unaligned data deallocation

In one or more embodiments, a NAND-based data storage device includes a device controller configured to receive a memory write command from a host specifying a set of memory locations to be written to, and to determine whether the command is for a random write. In response to the determination, the device controller is further configured to configure one or more update entries to an update layer of a mapping architecture of the device for the set of memory locations, such that the one or more update entries are respectively aligned with a size of a pre-defined MRU of mapping data for the device. By aligning the update entries with the smaller MRU, smaller regions of memory may be flagged as obsolete, increasing efficiency. In one embodiment, the device controller further includes a RAM, and the update layer is stored in the RAM.

Apparatus for obsolete mapping counting in NAND-based storage devices

A system and method for applying a first level of protection to data in a memory module include identifying a weak wordline from at least one of a plurality of blocks of the memory module. Each of the plurality of blocks includes a plurality of wordlines. The system and method also include determining that the weak wordline is to receive the first level of protection and applying the first level of protection to the weak wordline.

Partial XOR protection

Disclosed herein are related to a controller, a method, and a system for updating mapping information between a logical address and a physical address of a corresponding region of a memory device. In one aspect, the controller generates a plurality of entries, where each entry indicates an update in the mapping information associated with the corresponding region. The controller generates a plurality of headers, where each header is associated with one or more entries in the corresponding region. The controller receives an instruction to synchronize the mapping information stored on the memory device with the update in the mapping information. The controller generates a copy of the plurality of headers in response to receiving the instruction to synchronize. The controller synchronizes the mapping information stored on the memory device according to the copy of the plurality of headers and the plurality of entries.

Updating mapping information during synchronization of memory device

A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.

Scheduling scheme(s) for a multi-die storage device

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured, during execution of a relocation operation that includes storage of data to a memory buffer of an access device and retrieval of the data including data bits and first error correction code (ECC) parity bits from the memory buffer, to generate second ECC parity bits based on the data bits from the memory buffer and to compare the first ECC parity bits to the second ECC parity bits.

Data relocation

A system and method is described for managing mapping data in a non-volatile memory system having a volatile memory cache smaller than the update table for the mapping data. The system includes multiple mapping layers, for example two mapping layers, including a master mapping table of logical-to-physical mapping entries and an update table of mapping updates, for a non-volatile memory. A processor swaps predetermined size portions of the update mapping table and master mapping table into and out of the volatile memory cache based on host workload. The update mapping table portions may have a fixed or an adaptive logical range. Additional mapping layers, such as an expanded mapping layer having portions with a logical range greater than the logical range of the update mapping portions, may also be included and may be swapped into and out of the volatile memory with the master and update mapping table portions.

System and method for managing data in non-volatile memory systems having multiple mapping layers

Apparatuses, systems, methods, and computer program products are disclosed for address range mapping for memory devices. A system includes a set of non-volatile memory elements accessible using a set of physical addresses and a controller for the set of non-volatile memory elements. A controller is configured to maintain a hierarchical data structure for mapping logical addresses to a set of physical addresses. A hierarchical data structure comprises a plurality of levels with hashed mappings of ranges of logical addresses at range sizes selected based on a relative position of an associated level within the plurality of levels. A controller is configured to receive an I/O request for data of at least one logical address. A controller is configured to satisfy an I/O request using a hashed mapping having a largest available range size to map at least one logical address of the I/O request to one or more physical addresses.

Address range mapping for storage devices

Apparatus, systems, methods, and computer program products are disclosed for logical address range mapping for storage devices. A system includes a set of non-volatile memory elements accessible using a set of physical addresses. A system includes a controller for a set of non-volatile memory elements. A controller is configured to maintain a hierarchical data structure comprising a plurality of levels for mapping logical addresses to a set of physical address. A controller is configured to receive an input/output (I/O) request. A controller is configured to translate a logical address for an I/O request to a physical address utilizing a largest mapped logical address range that includes the logical address in a hierarchical data structure. A level includes one or more mappings between logical address ranges and physical address ranges at a range size for the level.

Logical address range mapping for storage devices

An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send control information to a host device. The control information is associated with first parity information. The controller further includes a circuit configured to determine second parity information associated with the control information. The controller is configured to terminate and optionally rollback an operation associated with the control information in response to the first parity information differing from the second parity information. The terminated optionally rolled-back operation associated with the control information may be a non-blocking control sync operation.

Techniques for non-blocking control information and data synchronization by a data storage device

A method that may be performed by a data storage device includes configuring the data storage device to use a first scheduling scheme and, in response to detecting a trigger event, configuring the data storage device to use a second scheduling scheme. One of the first scheduling scheme and the second scheduling scheme is used to schedule performance of memory operations having the same operation type at a plurality of dies of a memory of the data storage device. The other of the first scheduling scheme and the second scheduling scheme is used to schedule memory operations opportunistically.

Growing community of inventors

Bat Yam, Israel

Igor Genshaft