International Rectifier Corporation

Infineon Technologies Americas Corp.

Igor Bol

Iftikhar Ahmed

Ling Ma

Timothy Donald Henson

David Paul Jones

Niraj Ranjan

Hugo R Burke

Kapil Kelkar

Xin Li

Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

Method for fabricating a shallow and narrow trench FET and related structures

A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device includes a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one implementation, a method for fabricating a vertically arranged LDMOS device includes forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further includes diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body.

Method for fabricating a vertical LDMOS device

A process to thin semiconductor wafers to less than 50 microns employs a dissolvable photoresist or polyimide or other glue material to hold a thick carrier plate such as a perforated glass to the top surface of a thick processed wafer and to grind or otherwise remove the bulk of the wafer from its rear surface, leaving only the preprocessed top surface, which may include semiconductor device diffusions and electrodes. A thick metal such as copper or a more brittle copper alloy is then conductively secured to the ground back surface and the glue is dissolved and the carrier plate is removed. The wafer is then cleaned and diced into plural devices such as MOSFETs; integrated circuits and the like.

Process for manufacture of thin wafer

A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. The method further comprises diffusing impurities from the diffusion agent layer through the dielectric material to form a lightly doped drain region extending laterally around the sidewalls into the semiconductor body.

Vertical LDMOS device and method for fabricating same

A semiconductor die has devices such as MOSgated devices, diodes and the like formed into the top and bottom surfaces of the die. One terminal of each of the devices terminal in the interior center of the die and a common contact is made to the interior center of the die at one edge of the die. Various packages for the die having a reduced foot print on a support substrate are disclosed.

Double sided semiconduction device with edge contact and package therefor

A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.

Dynamic deep depletion field effect transistor

A method for manufacturing a power semiconductor device which includes forming a semiconductor region such as a polysilicon layer or epitaxially grown silicon over a region implanted with source implants and applying heat in a thermal step to cause the source implants to diffuse into the semiconductor region.

High density FET with self-aligned source atop the trench

An insulation is formed on a substrate of a material having a first conductivity type. A gate material is formed on the insulation. A portion of the gate material is removed thereby creating forming mesa type gate structures from remaining positions of the gate material. The mesas are then insulated. A channel forming layer, of a material having a second conductivity type, is formed between the produced mesas. Finally, a source of a material having the first conductivity type is formed on the channel forming layer.

Method for fabrication of MOSFET with buried gate

A termination structure and reduced mask process for its manufacture for either a FRED device or any power semiconductor device comprises at least two concentric diffusion guard rings and two spaced silicon dioxide rings used in the definition of the two guard rings. A first metal ring overlies and contacts the outermost diffusion. A second metal ring which acts as a field plate contacts the second diffusion and overlaps the outermost oxide ring. A third metal ring, which acts as a field plate, is a continuous portion of the active area top contact and overlaps the second oxide ring. The termination is useful for high voltage (of the order of 1200 volt) devices. The rings are segments of a common aluminum or Palladium contact layer.

Manufacturing process for fast recovery diode

A single mask process is described for making a trench type fast recovery process. The single mask defines slots in a photoresist for locally removing strips of nitride and oxide from atop silicon and for subsequently etching trenches in the silicon. A boron implant is carried out in the bottoms of the trenches to form local P/N junctions. The oxide beneath the nitride is then fully stripped in the active area and only partly stripped in the termination area in which the trenches are wider spaced than in the active area. Aluminum is then deposited atop the active area and in the trenches, but is blocked from contact with silicon in the active area by the remaining nitride layer.

Single mask trench fred with enlarged Schottky area

MOSFET with a buried gate

A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.

Low voltage planar power MOSFET with serpentine gate pattern

A single mask process for manufacture of a FRED employs a thick oxide layer over an N type silicon surface and a thin nitride layer over the oxide. A single mask defines FRED device spaced P diffusions. The oxide spanning the P diffusions is laterally etched away, under the nitride layer to expose the surface of adjacent P diffusions and the spanning N type silicon surface. All nitride is then removed and a top contact layer of aluminum is applied atop the silicon surface, contacting a P guard ring diffusion; the surface of the P diffusions defining PN junctions; and the top of the N silicon to define a Schottky diode contact.

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Sherman Oaks, CA, United States of America

Igor Bol