Lsi Corporation

Lsi Logic Corporation

Easic Corporation

Igor A Vikhliantsev

Alexander Andreev

Ranko L Scepanovic

Andrey Nikitin

Alexandre Andreev

Ivan Pavisic

Anatoli Aleksandrovich Bolotov

Sergey Vladimirovich Gribok

Vojislav Vukovic

Lav D Ivanovic

Ilya Vladimirovich Neznanov

Oleg N Izyumin

Chee-Wei Kung

Alexander Yahontov

Vojislav Vukovie

Mikhail Udovikhin

Chong-Teik Lim

Seow-Sung Lee

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller

A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Method and apparatus for generating memory models and timing database

A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a 'compute' logic block for computing a parity message (with sign) for application to related bit nodes and a 'compute' logic block for updating the data stored in the memory logic block for a next iteration of the LDPC decoder.

Circuits for implementing parity computation in a parallel architecture LDPC decoder

A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

A configurable low-density parity check code (LDPC) decoder and a method of configuring the decoder. In one embodiment, the configurable LDPC decoder includes: (1) pluralities of parity check units and bit node units, (2) direct and reverse multi-size barrel shifters coupled to the pluralities of parity check units and bit node units and (3) a control circuit, coupled to the pluralities of parity check units and bit node units and the direct and reverse multi-size barrel shifters and configured to configure sizes of the direct and reverse multi-size barrel shifters and numbers of the pluralities of parity check units and bit node units to cooperate therewith based on a block size of a particular LDPC code.

Configurable low-density parity-check decoder for LDPC codes of arbitrary block size and method of configuring the same

Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.

Methods and apparatus for programmable decoding of a plurality of code types

An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.

Parallel LDPC decoder

A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B'x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B&#x2032; is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.

Low complexity LDPC encoding algorithm

A Gaussian noise is simulated by discrete analogue r. A first parameter &#x3b1; and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude sis calculated for each point based on &#x3b1;, i and j. The discrete analogue ris based on a respective s. Examples are given of and D&#x3e;i&#x2267;0 and 2&#x3e;j&#x2267;0, where B&#x2267;0, 2&#x3e;A&#x3e;0, C&#x2267;1 and D&#x2267;1, and magnitude In some embodiments, a segment is defined based on &#x3b1; and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

Digital Gaussian noise simulator

A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.

High performance tiling for RRAM memory

Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time.

Methods and apparatus for fast unbalanced pipeline architecture

A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number, which establishes a de-serialization level for frequency reduction or phase shifting. An output provides an output data stream at the desired output frequency.

Data stream frequency reduction and/or phase shift

Digital gaussian noise simulator

Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. The coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.

Growing community of inventors

Sunnyvale, CA, United States of America

Igor A Vikhliantsev