Stmicroelectronics S.r.l.

Ignazio Martines

Michele La Placa

Davide Torrisi

Carmelo Condemi

Antonio Giambartino

Massimo Scardaci

Rino Micheloni

Marco MacCarrone

Jacopo Mulatti

Giacomo Curatolo

A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

Sense amplifier with reduced area occupation for semiconductor memories

A sensing circuit for a semiconductor memory, includes, a detecting amplifier including a first circuital branch is run through by a first current corresponding to the sum of a second current as a function of a comparison current and a cell current. The cell current is a function of a state of a memory cell to be read in a predetermined biasing condition. A second circuital branch is coupled as a current mirror configuration with the first circuital branch. The second circuital branch is run through by a third current proportional to the first current. A third circuital branch coupled to the second branch sinks a fourth current as a function of the comparison current. A fourth circuital branch coupled to is run through by a residual current equal to the difference between the third and the fourth current. The residual current assumes different values depending on the fact that the cell current is lower, equal or higher than the comparison current. A residual current sensitive means generates an indication of the state of the memory cell as a function of a value of the residual current.

Sense amplifier circuit and method for semiconductor memories with reduced current consumption

An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.

High speed CMOS output buffer for nonvolatile memory devices

An output buffer for providing a buffered current to a circuit load includes a plurality of operative stages, each one for generating a component of the buffered current and an enabling circuit for selectively enabling each operative stage. The output buffer further comprises at least one auxiliary stage and control means for measuring a control current that can be delivered by the at least one auxiliary stage and for activating the enabling means according to the measured control current.

Output buffer circuit and method with self-adaptive driving capability

A method for simultaneously programming a pre-established number of memory cells includes setting an initial number of memory cells to be simultaneously programmed equal to the pre-established number, and subdividing the initial number of memory cells to be programmed into subsets of memory cells. A program operation for simultaneously programming all the memory cells of each subset of memory cells is executed by forcing a current through all the memory cells of each subset of memory cells. The current has a program voltage associated therewith. The program voltage is compared to a threshold voltage during execution of the program operation. The method further includes stopping execution of the program operation if the threshold voltage is surpassed, reducing the initial number of memory cells to be simultaneously programmed, and restarting from the subdividing.

Method and circuit for simultaneously programming memory cells

The output buffer stage includes a half-bridge output stage having a first pair of complementary drivers connected in series between a supply line and a ground node, the high impedance state or conduction state of which is determined through a pair of control phases. The buffer stage includes a pair of switches controlled by the control phases, connected in series between them and connecting the transistors of the first stage in series. Each driver is connected in series with a switch, that is quickly opened to prevent under-threshold currents from circulating when the respective driver is turned off, and that is rapidly turned off when the respective driver is turned on.

Output buffer stage

A bit-line selection circuit for a memory device includes a decoding line and a dummy line: The decoding line is between a regulated voltage node, and a programming voltage node generating a programming voltage for a cell in the memory device. The decoding line includes at least one input transistor connected to the regulated voltage node, and is controlled by an enable/disable signal. The dummy line is identical to the decoding line, and is controlled by the enable/disable signal. An equalization circuit is connected between the decoding and dummy lines for setting a current in the dummy line equal to a current in the decoding line. A regulating circuit regulates the programming voltage generated at the programming voltage node in the decoding line. The regulating circuit has a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in the dummy line, and an output for providing the enable/disable signal. The regulating circuit compensates for differences between the programming voltage and the reference voltage.

Circuit for selecting/deselecting a bitline of a non-volatile memory

Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents of the array memory cell. The method envisages reducing the electrical stress to which the reference memory cell is subjected during reading, by generating and holding a sample of the reference voltage, then deselecting the reference memory cell, and then continuing reading using the sample of the reference voltage.

Reading circuit and method for a nonvolatile memory device

A circuit verifies and substitutes a defective reference cell of a memory device that includes at least one reference current path including the reference cell and a decoding transistor connected in series. The circuit includes at least one redundant reference current path identical to the at least one reference current path and in parallel therewith. A connection circuit connects in a mutually exclusive way control terminals of the decoding transistor and reference cell of the at least one reference current path to a node or control terminals of the decoding transistor and reference cell of the at least one redundant reference current path to the node. The connecting is based upon a logic signal. A window comparator is coupled to the reference current path for comparing a current therein with a pair of upper and lower thresholds, and outputs the logic signal for the connection circuit based upon the comparison.

Method and circuit for verifying and eventually substituting defective reference cells of a memory

The invention relates to a voltage regulation system for multiword programming in non volatile memories, for example of the Flash type, with low circuit area occupation, wherein memories comprise at least a memory cell matrix organized in cell rows and columns and with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. The memory cells have drain terminals connected to matrix columns and are biased in the programming step with a predetermined voltage value by means of program load circuits associated to each matrix column. In parallel with each program load circuit, a conduction-to-ground path is enabled by a controlled active element.

Voltage regulation system for a multiword programming of a low integration area non volatile memory

A plurality of non volatile memory cells, for example of the flash type, with low circuit area occupation, are organized in cell matrices with corresponding circuits responsible for addressing, decoding, reading, writing and erasing the memory cell content. Each of the cells has a gate terminal biased in the programming phase with a predetermined voltage value through operation of charge pump voltage regulators. A first and a second regulation stage, which are structurally independent, are responsible for the programming and soft programming phase respectively. The first stage generates a supply voltage for the second stage.

Gate voltage regulation system for a non-volatile memory cells programming and/or soft programming phase

An output buffer for causing a voltage (Vout) of an integrated circuit output line (OUT,OUT_PAD) to switch from a voltage of a first voltage line (VDD) to a voltage of a second voltage line (GND) and vice versa, comprises a current path switch circuit ( ) activatable for causing a prescribed current (Is) to constantly flow between the first and second voltage lines during a time between two successive switchings of the output line, and for causing the prescribed current to be deviated (Ic ) to the output line during at least an initial phase of an output line switching from the first voltage line voltage to the second voltage line voltage or vice versa. A current delivered by the first and second voltage lines is thus kept substantially constant in the output line switching. In this way, the time derivative of the current flowing between the first and the second voltage lines is kept small and low switching noise is induced.

Low-noise output buffer

A negative charge pump circuit includes a cascade connection of a plurality of charge pump stages, each stage including at least a charge capacitance and a pass transistor driven by a corresponding phase signal. An input stage may be coupled to an input reference potential. An output stage may include an output terminal for generating a first pumped voltage. In addition, the charge pump circuit may further include a second output stage connected downstream to the input stage and including a second output terminal for generating a second pumped potential. The architecture may also be implemented in positive charge pump circuits.

Negative charge pump architecture with self-generated boosted phases

A circuit for generating a constant pulse signal from an enabling ATD input signal may include a latch structure connected between first and second circuit nodes, with each node being coupled to a corresponding charge and discharge capacitance and being also connected to respective inputs of a logic gate. The circuit may also include a memory element coupled to the circuit nodes for filtering the enabling ATD signal and avoiding a partial discharge of one of the capacitances. An output of the logic gate is provided for generating the pulse signal independent of voltage and/or temperature variations affecting the enabling ATD signal.

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Tremestieri Etneo, Italy

Ignazio Martines