Stmicroelectronics S.r.l.

Ignazio Bruno Mirabella

Salvatore Pappalardo

Francesco Pulvirenti

Alessandro Nicolosi

Agatino Antonino Alessandro

Calogero Ribellino

A power transistor supplying power to a load is coupled to a current limiter circuit including a differential amplifier that operates to detect a difference between a sense voltage, indicative of a load current, and a voltage reference. A control terminal of the power transistor is driven by a first output of the differential amplifier as a function of the detected difference. A voltage clamp circuit coupled to an input terminal generates a floating ground. A short-circuit protection circuit coupled to the floating ground and interposed between a second output of the differential amplifier and the control terminal of the power transistor provides a short-circuit protection for the first output of the differential amplifier. A reaction time circuit is coupled between the first and second outputs of the differential amplifier and a source terminal of the power transistor to limit a short-circuit current at the source terminal.

Current limiter, corresponding device and method

A level-shifter circuit operates to shift an input signal referenced to a first set supply voltages to generate an output signal referenced to a second set of supply voltages. The output signal from the level-shifter circuit is latched by a latching circuit. A logic gate has a first input configured to receive the input signal, a second input configured to receive a feedback signal and an output coupled to a input of the level shifting circuit. A feedback circuit has a first input configured to receive the output signal, a second input configured to receive the input signal and an output configured to generate the feedback signal. The feedback circuit operates to sense an uncontrolled switching event of the output signal occurring in the absence of a switching of the input signal and apply, in response thereto, the feedback signal to cancel the uncontrolled switching event.

Level shifter circuit, corresponding device and method

First and second comparators receive input signals of opposed polarities and drive operation of a switch in response thereto. A first current generator supplies a first current to the switch which, in response to the control of the first and second comparators, applies the first current, alternatively, to a first node or a second node. A second current generator sinks a second current from the first node and a third current generator sinks a third current from the second node. A logic circuit has inputs coupled to the first node and the second node, respectively, receives respective switching signals having fast switching wavefronts and delayed switching wavefronts. The output of logic circuit is configured for switching between a first state and a second state with switching between the first state and the second state triggered by the fast switching wavefronts of the respective switching signals.

High-voltage switching circuit, corresponding device and method

A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the semiconductor chip, and structures for protection from radiation for protecting the integrated circuit from ionizing radiation. The structures for protection from radiation include a protective layer of gel, which occupies at least in part the cavity and coats the semiconductor chip.

Radiation-hard electronic device and method for protecting an electronic device from ionizing radiation

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

Memory cell and corresponding device

A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first voltage reference and an output stage configured to generate an output signal referenced to a second voltage reference (different from the first voltage reference) in response to the intermediate signal.

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Scicli, Italy

Ignazio Bruno Mirabella