Chips and Technologies, Llc.

Other

S3 Incorporated, Inc.

Ignatius B Tjandrasuwita

James E Margeson, Iii

William S Herz

Reena Premi

A apparatus to generate gray scale shading data in response to input color data that is cost efficient and programmable is presented. The present invention allows up to 16 brightness-levels to be generated per color (e.g., Red, Green, and Blue). Under the present invention, each color pixel can be programmed to have one of the 16 brightness-level waveforms stored in a memory by dynamically changing a number of variables such as pixel color offsets, frame offset, column offset, row offset, pixel mapping data, etc. An accessing waveform index is generated from the above variables which is then used to select a brightness-level waveform from the memory. The brightness-level waveforms stored in the memory are also programmable.

&ldquo;Frame-rate modulation method and apparatus to generate flexible grayscale shading for super twisted nematic displays using stored brightness-level waveforms&rdquo;

Data stream converter with increased grey levels

A device performs both 2-tap and 3-tap flicker filtering of non-interlaced lines of computer graphics data to form interlaced lines. The device includes a data packer, a data unpacker, and a filter circuit. The filter circuit combines lines that it receives to form filtered lines. The data packer writes the filtered lines to line buffers while the data unpacker reads the lines stored in the line buffers. The read lines are either sent to the filter circuit for further filtering or are outputted to be displayed as interlaced lines. Both 2-tap and 3-tap flicker filtering can be accomplished by varying the order and/or number of read, write, and filter operations.

System and methods for both 2-tap and 3-tap flicker filtering of

A clock gating apparatus that is cost efficient and allows power conservation is presented. The clock gating apparatus is implemented to allow data paths, that are used to process data, to be enabled or disabled as desired while preventing the clock-skew problem. The clock gating apparatus includes a plurality of clock gating circuits, wherein one clock gating circuit is implemented for each data path. In a first embodiment, while all the data paths propagate data in a first direction and eventually merge together at a node, the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction. In a second embodiment, parallel data paths that are mutually exclusive of each other propagate data in a first direction and the clock gating circuits are connected together in a cascaded fashion to propagate a clock signal in a second direction opposite from the first direction.

Data path clock skew management in a dynamic power management environment

A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. In so doing, a graphics controller can operate within its intended specification while operating at the same clock frequency whether in CRT or multi-segment mode. In addition, this architecture overcomes the other problems associated with prior art graphics controllers.

Frame buffer with matched frame rate

The present invention relates to An apparatus for converting cathode ray tube (CRT) to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.

Growing community of inventors

Union City, CA, United States of America

Ignatius B Tjandrasuwita