Intel Corporation

Mellanox Technologies, Ltd.

Apple Inc.

Other

Mellanox Technologies Tlv Ltd.

Igal Kushnir

Ofir Degani

Gil Horovitz

Rotem Banin

Elan Banin

Eshel Gordon

Yossi Tsfati

Ashoke Ravi

Evgeny Shumaker

Sidharth Dalmia

Sarit Zur

Shmuel Ravid

Aryeh Farber

Noam Kogan

Roi Levi

Kameran Azadet

Shilpa Talwar

Hosein Nikopour

Bryan K Casper

Wook Bong Lee

Michael Genossar

Claudio Da Silva

Stefano Pellerano

Debabani Choudhury

Albert Molina

Georgios Yorgos Palaskas

Duncan Kitchin

Saku Lahti

Oner Orhan

Emanuel Cohen

Mikko S Komulainen

Gadi Shor

Eren Sasoglu

Jayprakash Thakur

Arnaud Lucres Amadjikpe

Menashe Soffer

Ana M Yepes

Kunal Datta

Omer Asaf

Moshe Teplitsky

Run Levinger

Chintan S Thakkar

Josef Hagn

Erkan Alpman

Tawfiq Musah

Baljit Singh

Nebil Tanzi

Ron Pongratz

Peter Sagazio

Amit Freiman

Eyal Goldberger

Kaushik Dasgupta

Eran Gerson

Sharon Malevsky

Marian K Verhelst

Meir Gordon

Nir Weisman

Resti Montoya Moreno

Shuhei Yamada

Anandaroop Chakrabarti

Miroslav Baryakh

Ra'anan Sover

Naftali Landsberg

Ayal Eshkoli

Mikko M Lampinen

Lior Shakedd

Avi Tsarfati

Anat Bazov

Stefano Brenna

Saeid Daneshgar Asl

Amr M Fahim

Shinwon Kang

Te Yu Kao

Nathan G Narevsky

Eng Hun Ooi

Eytan Mann

Shahar Porat

Amir Israel Rubin

Ran Shimon

Gregory Chance

Ronen Gernizky

Nisim Machluf

Vladimir Volokitin

Elinor Kashani

Brandon Davis

Dmitry Felsenstein

Bernhard Raaf

Harry G Skinner

Alexandros Margomenos

Assaf Ben-Bassat

Gregory W Chance

Alon Cohen

Brandon R Davis

Benjamin Jann

Tal Davidson

Raanan Sover

Ronen Kronfeld

Lior Kravitz

Satwik Patnaik

Sergey Bershansky

Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.

C2C yield and performance optimization in a die stacking platform

Technologies for duty cycle distortion (DCD) estimation are described. A transmitter includes a first output driver comprising a first complementary metal-oxide semiconductor (CMOS) amplifier and a first attenuator coupled to an output of the first CMOS amplifier. The first CMOS amplifier receives an input signal and outputs an intermediate signal to the first attenuator. The first attenuator receives the intermediate signal and outputs an output signal having a signal swing that is less than a signal swing of the input signal. A first duty cycle correction (DCC) loop is coupled to the first output driver. The first DCC loop estimates first DCD in the intermediate signal output by the first CMOS amplifier.

Duty cycle distortion (DCD) sampling in a low-swing transmitter

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

Wireless communication technology, apparatuses, and methods

A method and apparatus for generating a frequency-modulated continuous wave (FMCW) signal. The apparatus may include a first oscillator configured to generate a first oscillation signal, a frequency modulator configured to generate a frequency-modulated oscillation signal from the first oscillation signal based on a sequence of control words, a frequency modulation code generator configured to generate a sequence of frequency modulation codes for generating an FMCW waveform, and a frequency multiplier configured to generate the FMCW signal by up-converting the frequency-modulated oscillation signal. The sequence of control words is generated based on the sequence of frequency modulation codes. The apparatus may include a second oscillator configured to generate a second oscillation signal, and a phase detector configured to detect a phase difference between the first oscillation signal and the second oscillation signal and generate an offset code based on the phase difference. The frequency modulator may be a digital-to-time converter.

Method and apparatus for generating frequency modulated continuous wave signal

A system includes a first device, coupled to a link, which transmits a signal having a repeating pattern on one or more paths of the link. The system includes a second device coupled to the link and including one or more circuits and a time-to-digital converter (TDC). The second device is to receive at the one or more circuits the signal. The second device is to determine, by the TDC, a current duty cycle of the signal, the current duty cycle having a first duration associated with a first portion of the signal and a second duration associated with a second portion of the signal. The second device is further to determine the current duty cycle fails to satisfy a condition associated with a target duty cycle in response to determining the current duty cycle of the signal and adjust the current duty cycle to obtain an adjusted duty cycle.

Signal distortion correction with time-to-digital converter (TDC)

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

Time encoded data communication protocol, apparatus and method for generating and receiving a data signal

Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.

Systems and methods for calibrating digital phase-locked loops

Examples relate to a digitally controlled oscillator circuit arrangement, a digitally controlled oscillation means, a method for a digitally controlled oscillator, a digital loop filter circuit arrangement, a digital loop filtering means, a method for a digital loop filter, a phase locked loop circuit arrangement and phase locked loop, a user device and a base station. The digitally controlled oscillator circuit arrangement comprises input circuitry for obtaining a frequency setting signal, the frequency setting signal comprising a plurality of signal components, selection circuitry for selecting one signal component of the plurality of signal components of the frequency setting signal based on an oscillation signal of the digitally controlled oscillator circuit arrangement, wherein the selection circuitry comprises counting circuitry and multiplexing circuitry, signal generation circuitry for generating the oscillation signal based on the selected signal component of the frequency setting signal, and output circuitry for providing the oscillation signal.

Concept for a digital controlled loop and a digital loop filter

A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

Systems, methods, and devices for digital-to-analog conversion in data transmission

An apparatus for generating an oscillation signal is provided. The apparatus includes a first oscillator configured to generate a first reference oscillation signal, and a second oscillator configured to generate a second reference oscillation signal. A frequency accuracy of the first oscillator is higher than a frequency accuracy of the second oscillator. Further, an oscillator phase noise of the second oscillator is lower than an oscillator phase noise of the first oscillator. The apparatus further includes a processing circuit configured to generate a third reference oscillation signal based on the first reference oscillation signal and the second reference oscillation signal. Additionally, the apparatus includes a phase-locked loop configured to generate the oscillation signal based on the third reference oscillation signal. A frequency of the oscillation signal is a multiple of a frequency of the third reference oscillation signal.

Apparatuses for generating an oscillation signal

An electrical device () that comprises at least one signal filter () comprising a plurality of mechanical resonators () in a substrate () and at least one further mechanical resonator () in the substrate () configured to oscillate at a reference frequency of an oscillator signal. An electrical system () comprising an electrical oscillator () a transceiver () and an antenna (), and an electrical device (). A method () for providing an electrical device ().

Electrical device, electrical system with an electrical device and method to provide an electrical device

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Hod-Hasharon, Israel

Igal Kushnir