Intel Corporation

Ido Melamed

Efraim Rotem

Eliezer Weissmann

Alexander Gendler

Nir Rosenzweig

Yoni Aizik

Doron Rajwan

Nadav Shulman

Guy M Therien

Esfir Natanzon

Arik Gihon

Yevgeni Sabin

Paul S Diefenbaugh

Barnes Cooper

Michael Mishaeli

Hisham Abu Salah

Nimrod Angel

Chen Ranel

Niv Tokman

Natanel Abitan

Krishnakanth Venkata Sistla

Avinash N Ananthakrishnan

Ankush Varma

Vivek Garg

Shaun M Conrad

Tomer Ziv

Ariel Szapiro

Christopher J Lake

Adwait Purandare

Israel Hirsh

Hem Doshi

Elkana Korem

Eric Dehaemer

Yoav Ben-Raphael

Arye Albahari

Nir Misgav

Edward Vaiberman

Reena Patel

Vijay Degalahal

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.

Autonomous core perimeter for low power processor states

In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.

Controlling a performance state of a processor using a combination of package and thread hint information

In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Forcing a processor into a low power state

Growing community of inventors

Kfar-Saba, Israel

Ido Melamed