Mellanox Technologies, Ltd.

Idan Burstein

Noam Bloch

Liran Liss

Ariel Shahar

Michael Kagan

Yamin Friedman

Diego Crupnicoff

Shlomo Raikin

Miriam Menes

Roee Moyal

Hillel Chapman

Yuval Shpigelman

Adi Menachem

Dror Goldenberg

Dotan David Levi

Boris Pismenny

Aviad Shaul Yehezkel

Peter Paneah

Lior Narkis

Gal Yefet

Rabia Loulou

Maxim Fudim

Mark B Rosenbluth

Ilan Pardo

Eitan Zahavi

Daniel Marcovitch

Matty Kadosh

Yaron Haviv

Shachar Raindel

Haggai Eran

Shay Aisman

Michael Weiner

Dror Bohrer

Igor Voks

Tzah Oved

Ron Yuval Efraim

Achiad Shochat

Tzahi Oved

Alexander Eli Rosenbaum

Gil Levy

Barak Gafni

Liron Mula

Aviv Kfir

Benny Koren

Zachy Haramaty

Avi Urman

Avraham Ganor

Ariel Almog

Ariel Shachar

Niv Aibester

Oded Lempel

Lavi Koch

Alex Shpiner

Oren Duer

Omer Shabtai

Eliav Bar-Ilan

Amir Ancel

Ran Avraham Koren

Michael Cotsford

Rui Xu

Gil Kremer

Gary Mataev

Aviv Barnea

Tzuriel Katoa

Richard Hastie

Charlie Mbariky

Tsofia Eshel

Rotem Levinson

Yossi Kendel

Aviv Heller

Arie Shahar

Reut Zuck

Shlomi Museri

Amit Hermony

A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The one or more ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to identify a memory-access congestion, which occurs in accessing the shared memory by one or more of the processing tasks, and to alleviate the memory-access congestion by causing a reduction in a communication rate of at least one of the packet flows.

Alleviating memory-access congestion in network devices

A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

Cross address-space bridging

Methods, systems, and computer program products for selecting packing processing cores are provided. An example system includes a plurality of packet processing cores and a load balancing unit communicatively connected to the plurality of packet processing cores. The load balancing unit is configured to receive a workflow packet including packet description data indicative of at least a packet structure and a packet priority and receive, from the plurality of packet processing cores, state data indicative of at least a utilization state and an operating state of each of the respective packet processing cores. The load balancing unit determines a selected packet processing core from amongst the plurality of packet processing cores based on the state data of the packet processing core and the packet description data of the workflow packet and transmits the workflow packet to the selected packet processing core.

Methods, systems, and computer program products for dynamic load balancing

In one embodiment, a secure distributed processing system includes nodes connected over a network, and configured to process tasks, each respective one of the nodes including a respective processor to process data of respective ones of the tasks, and a respective network interface controller to connect to other nodes over the network, store task master keys for use in computing communication keys for securing data transfer over the network for respective ones of the tasks, compute respective task and node-pair specific communication keys for securing communication with respective ones of the nodes over the network for respective ones of the tasks responsively to respective ones of the task master keys and node-specific data of respective node pairs, and securely communicate the processed data of the respective ones of the tasks with the respective ones of the nodes over the network responsively to the respective task and node-pair specific communication keys.

Secure and efficient distributed processing

A network adapter includes a port and one or more circuits. The port is to send packets to a network in accordance with a Remote Direct Memory Access over Converged Ethernet (RoCE) protocol. The one or more circuits are to decide whether a packet is permitted to undergo Adaptive Routing (AR) in being routed through the network, to mark the packet with an indication of whether the packet is permitted to undergo AR, and to send the marked packet to the network via the port.

Marking of RDMA-over-converged-ethernet (RoCE) traffic eligible for adaptive routing

A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.

Methods and systems for limiting data traffic while processing computer system operations

Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

Multi-socket network interface controller with consistent transaction ordering

Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.

Session-based remote direct memory access

A method and system are provided for limiting unnecessary data traffic on the data communication connections connecting various system components, including the various levels of system memory. Some embodiments may include processing a buffer allotment request and/or a buffer release command in coordination with a system or network operation requiring temporary storage of data in a memory buffer. The buffer allotment request may be capable of indicating the amount of storage space required on the memory buffer to execute the system or network operation. The system may be capable of precluding the system or network operation from executing until there is sufficient space in the memory buffer to complete the operation without evicting operational data from the memory buffer. In some embodiments, the buffer release command may signal completion of the system or network operation and release of the utilized memory buffer space for other operations.

Methods and systems for managing memory buffer usage while processing computer system operations

A network adapter includes a port and one or more circuits. The port communicates packets over a network in which switches forward packets in accordance with tuples of the packets. The one or more circuits are to hold a user-programmable scheme specifying assignments of the packets of a given flow destined to a peer node to sub-flows having respective different tuples, assign first packets of the given flow to one or more of the sub-flows in accordance with the user-programmable scheme, by setting respective tuples of the first packets, transmit the first packets to the peer node via the port, monitor notifications received from the network, the notifications being indicative of respective states of the sub-flows, based on the notifications and on the user-programmable scheme determine an assignment of second packets of the given flow to the sub-flows, and transmit the second packets to the peer node via the port.

Flexible per-flow multipath managed by sender-side network adapter

An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.

Handling of out-of-order transport-layer packets using reorder buffer

A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

Cross network bridging

Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

Data processing unit with transparent root complex

Growing community of inventors

Karmiel, Israel

Idan Burstein